| Message ID | 20240926141956.2386374-1-alvinzhou.tw@gmail.com |
|---|---|
| Headers | show |
| Series | Add octal DTR support for Macronix flash | expand |
On Thu, 26 Sep 2024 22:19:50 +0800, AlvinZhou wrote: > Add method for Macronix Octal DTR Enable/Disable. > Merge Tudor's patch "Allow specifying the byte order in DTR mode" > > v10: > * Further explanation on adding Macronix manufacturer ID in ID table. > * Correct some typos. > > [...] Made the changes that I specified in replies. SFDP "Command Sequences to Change to Octal DDR (8D-8D-8D) Mode" can be parsed later on. Applied to git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git, spi-nor/next branch. Thanks! [1/6] mtd: spi-nor: add Octal DTR support for Macronix flash https://git.kernel.org/mtd/c/ccac858d2bdb [2/6] spi: spi-mem: Allow specifying the byte order in Octal DTR mode https://git.kernel.org/mtd/c/030ace430afc [3/6] mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode https://git.kernel.org/mtd/c/6a42bc97ccda [4/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT https://git.kernel.org/mtd/c/46b6256a68b4 [5/6] spi: mxic: Add support for swapping byte https://git.kernel.org/mtd/c/50cb86f21ec2 [6/6] mtd: spi-nor: add support for Macronix Octal flash https://git.kernel.org/mtd/c/afe1ea1344bb Cheers,
From: AlvinZhou <alvinzhou@mxic.com.tw> Add method for Macronix Octal DTR Enable/Disable. Merge Tudor's patch "Allow specifying the byte order in DTR mode" v10: * Further explanation on adding Macronix manufacturer ID in ID table. * Correct some typos. v9: * Change the name of the configuration register 2 for Macronix Octal flash. * Fix the bit value in __pad of struct spi_mem_op. * Use the local variable proto instead of nor->read_proto. v8: * Supplement missing S-o-b * Remove function spi_nor_is_octal_dtr_swab16 * Split IDs by MX25 & MX66 * Add dump of capability in debugfs * Add dump of parameters in debugfs * Add dump of result for mtd-utils tests * Add SNOR_ID(0xC2) in last of Macronix ID table v7: * Add dtr_swab16 judgement to enable/disable Macronix xSPI host controller swap byte feature. v6: * Add byte swap support for spi-mxic.c * Remove flash name in ID table. v5: * Remove manufacturer read id function. * For increased readability, separate Flash IDs based on whether it supports RWW feature. v4: * Add patch for adding manufacturer read id function. remove patch "hook manufacturer by checking first byte id" v3: * Add patch for hook manufacturer by comparing ID 1st byte. * Add patches for specifying the byte order in DTR mode by merging Tudor's patch. v2: * Following exsiting rules to re-create Macronix specify Octal DTR method. * change signature to jaimeliao@mxic.com.tw * Clear sector size information in flash INFO. AlvinZhou (6): mtd: spi-nor: add Octal DTR support for Macronix flash spi: spi-mem: Allow specifying the byte order in Octal DTR mode mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT spi: mxic: Add support for swapping byte mtd: spi-nor: add support for Macronix Octal flash drivers/mtd/spi-nor/core.c | 4 ++ drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/macronix.c | 95 +++++++++++++++++++++++++++++++++- drivers/mtd/spi-nor/sfdp.c | 4 ++ drivers/mtd/spi-nor/sfdp.h | 1 + drivers/spi/spi-mem.c | 3 ++ drivers/spi/spi-mxic.c | 17 ++++-- include/linux/spi/spi-mem.h | 8 ++- 8 files changed, 127 insertions(+), 6 deletions(-)