| Message ID | 20240718075356.488253-1-linchengming884@gmail.com |
|---|---|
| Headers | show |
| Series | Add fixups for two-plane serial NAND flash | expand |
Hi Cheng, linchengming884@gmail.com wrote on Thu, 18 Jul 2024 15:53:54 +0800: > From: Cheng Ming Lin <chengminglin@mxic.com.tw> > > Macronix serial NAND flash with a two-plane structure > requires insertion of Plane Select bit into the column > address during the write_to_cache operation. > > Additionally, for MX35{U,F}2G14AC, insertion of Plane > Select bit into the column address is required during > the read_from_cache operation. I guess if the plane bit is needed for your chips, it is also needed for other whips with two planes? Could it be possible that we never had support for devices with more than one plane and you just fall into a common issue? Maybe we should always add the plane information when there is more than one plane to address? Can you check whether this is specific to Macronix or not? In this case we wouldn't need a specific fixup. > > These flashes have been validated on Xilinx zynq-picozed > board which included Macronix SPI Host. > > Cheng Ming Lin (2): > mtd: spinand: Add fixups for spinand > mtd: spinand: macronix: Fixups for Plane Select bit > > drivers/mtd/nand/spi/core.c | 7 ++++ > drivers/mtd/nand/spi/macronix.c | 66 ++++++++++++++++++++++++++++++--- > include/linux/mtd/spinand.h | 17 +++++++++ > 3 files changed, 84 insertions(+), 6 deletions(-) > Thanks, Miquèl
Hi Miquel, Miquel Raynal <miquel.raynal@bootlin.com> 於 2024年8月12日 週一 下午4:56寫道： > > Hi Cheng, > > linchengming884@gmail.com wrote on Thu, 18 Jul 2024 15:53:54 +0800: > > > From: Cheng Ming Lin <chengminglin@mxic.com.tw> > > > > Macronix serial NAND flash with a two-plane structure > > requires insertion of Plane Select bit into the column > > address during the write_to_cache operation. > > > > Additionally, for MX35{U,F}2G14AC, insertion of Plane > > Select bit into the column address is required during > > the read_from_cache operation. > > I guess if the plane bit is needed for your chips, it is also needed > for other whips with two planes? Could it be possible that we never had > support for devices with more than one plane and you just fall into a > common issue? Maybe we should always add the plane information when > there is more than one plane to address? Can you check whether this is > specific to Macronix or not? > I have reviewed the chips listed by each vendor. Micron offers MT29F2G01AB{A,B}GD, MT29F2G01AAAED with two planes; however, only MT29F2G01AAAED requires the plane select bit when performing program load or read from cache. Link: https://semiconductors.es/pdf-down/M/T/2/MT29F2G01AAAED-MicronTechnology.pdf Winbond provides W25N04KV with two planes, but it does not require the plane select bit for program load or cache read operations. Therefore, we should not always include the plane select bit when dealing with multiple planes. > In this case we wouldn't need a specific fixup. > Based on the above perspective, do we still need to use fixup, or can we use flags to determine whether the plane select bit is necessary? > > > > These flashes have been validated on Xilinx zynq-picozed > > board which included Macronix SPI Host. > > > > Cheng Ming Lin (2): > > mtd: spinand: Add fixups for spinand > > mtd: spinand: macronix: Fixups for Plane Select bit > > > > drivers/mtd/nand/spi/core.c | 7 ++++ > > drivers/mtd/nand/spi/macronix.c | 66 ++++++++++++++++++++++++++++++--- > > include/linux/mtd/spinand.h | 17 +++++++++ > > 3 files changed, 84 insertions(+), 6 deletions(-) > > > > > Thanks, > Miquèl Thanks, ChengMing Lin
Hi Cheng, linchengming884@gmail.com wrote on Tue, 13 Aug 2024 14:02:44 +0800: > Hi Miquel, > > Miquel Raynal <miquel.raynal@bootlin.com> 於 2024年8月12日 週一 下午4:56寫道： > > > > Hi Cheng, > > > > linchengming884@gmail.com wrote on Thu, 18 Jul 2024 15:53:54 +0800: > > > > > From: Cheng Ming Lin <chengminglin@mxic.com.tw> > > > > > > Macronix serial NAND flash with a two-plane structure > > > requires insertion of Plane Select bit into the column > > > address during the write_to_cache operation. > > > > > > Additionally, for MX35{U,F}2G14AC, insertion of Plane > > > Select bit into the column address is required during > > > the read_from_cache operation. > > > > I guess if the plane bit is needed for your chips, it is also needed > > for other whips with two planes? Could it be possible that we never had > > support for devices with more than one plane and you just fall into a > > common issue? Maybe we should always add the plane information when > > there is more than one plane to address? Can you check whether this is > > specific to Macronix or not? > > > > I have reviewed the chips listed by each vendor. > > Micron offers MT29F2G01AB{A,B}GD, MT29F2G01AAAED with two planes; > however, only MT29F2G01AAAED requires the plane select bit when performing > program load or read from cache. > > Link: https://semiconductors.es/pdf-down/M/T/2/MT29F2G01AAAED-MicronTechnology.pdf > > Winbond provides W25N04KV with two planes, but it does not require the plane > select bit for program load or cache read operations. > > Therefore, we should not always include the plane select bit when dealing with > multiple planes. > > > In this case we wouldn't need a specific fixup. > > > > Based on the above perspective, do we still need to use fixup, or can we use > flags to determine whether the plane select bit is necessary? I still prefer flags rather than invasive fixup hooks. > > > > > > > These flashes have been validated on Xilinx zynq-picozed > > > board which included Macronix SPI Host. > > > > > > Cheng Ming Lin (2): > > > mtd: spinand: Add fixups for spinand > > > mtd: spinand: macronix: Fixups for Plane Select bit > > > > > > drivers/mtd/nand/spi/core.c | 7 ++++ > > > drivers/mtd/nand/spi/macronix.c | 66 ++++++++++++++++++++++++++++++--- > > > include/linux/mtd/spinand.h | 17 +++++++++ > > > 3 files changed, 84 insertions(+), 6 deletions(-) > > > > > > > > > Thanks, > > Miquèl > > Thanks, > ChengMing Lin Thanks, Miquèl
From: Cheng Ming Lin <chengminglin@mxic.com.tw> Macronix serial NAND flash with a two-plane structure requires insertion of Plane Select bit into the column address during the write_to_cache operation. Additionally, for MX35{U,F}2G14AC, insertion of Plane Select bit into the column address is required during the read_from_cache operation. These flashes have been validated on Xilinx zynq-picozed board which included Macronix SPI Host. Cheng Ming Lin (2): mtd: spinand: Add fixups for spinand mtd: spinand: macronix: Fixups for Plane Select bit drivers/mtd/nand/spi/core.c | 7 ++++ drivers/mtd/nand/spi/macronix.c | 66 ++++++++++++++++++++++++++++++--- include/linux/mtd/spinand.h | 17 +++++++++ 3 files changed, 84 insertions(+), 6 deletions(-)