Message ID | 20231108-fix-mips-nand-v1-0-5fc5586d04de@linaro.org |
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Wed, 08 Nov 2023 06:33:56 -0800 (PST) From: Linus Walleij <linus.walleij@linaro.org> Subject: [PATCH 0/6] Fix polarity and bindings for GPIO-based NAND drivers Date: Wed, 08 Nov 2023 15:33:48 +0100 Message-Id: <20231108-fix-mips-nand-v1-0-5fc5586d04de@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAEycS2UC/x2MQQqAIBAAvyJ7bkGtoPpKdDBdaw+ZKEQg/j3pO DAzBTIlpgyLKJDo4cx3aKA6AfY04SBk1xi01L1SckTPL14cMwYTHNpZ0e4m6c3goTUxURP+37r V+gEN+7w/XwAAAA== To: Aaro Koskinen <aaro.koskinen@iki.fi>, Janusz Krzysztofik <jmkrzyszt@gmail.com>, Tony Lindgren <tony@atomide.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Thomas Bogendoerfer <tsbogend@alpha.franken.de>, Ben Dooks <ben.dooks@codethink.co.uk> Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, Linus Walleij <linus.walleij@linaro.org>, Howard Harte <hharte@magicandroidapps.com> X-Mailer: b4 0.12.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231108_063401_765381_BA13F1C1 X-CRM114-Status: GOOD ( 14.80 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The AMD Delta and generic GPIO-based NAND drivers are using GPIO lines extensively to communicate with a raw NAND flash. Some confusion has crept into the naming leading to the two drivers using inversed semantics differently for pins with the same name. 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Fix polarity and bindings for GPIO-based NAND drivers
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The AMD Delta and generic GPIO-based NAND drivers are using GPIO lines extensively to communicate with a raw NAND flash. Some confusion has crept into the naming leading to the two drivers using inversed semantics differently for pins with the same name. Fix the situation by naming the pins consistently without any inversion names (such as nce for a negative active chip enable). Fix up all in-tree users. Next rewrite the device tree bindings in YAML schema, and fix up the single in-tree DTS file (MIPS) to use the new bindings where each signal is specified explicitly instead of an array with some "blanks" for unused lines. Last clean up the GPIO NAND driver to drop use of board file provided data as no boards using this remain, and use device properties removing the explicit reliance on device tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- Linus Walleij (6): mtd: rawnand: ams-delta/gpio: Unify polarity dt-bindings: mtd: Rewrite gpio-control-nand in schema MIPS: NI 169445: Fix NAND GPIOs mtd: rawnand: gpio: Use device properties mtd: rawnand: gpio: Support standard nand width mtd: rawnand: gpio: Rename file .../devicetree/bindings/mtd/gpio-control-nand.txt | 47 ------ .../devicetree/bindings/mtd/gpio-control-nand.yaml | 168 +++++++++++++++++++++ Documentation/devicetree/bindings/mtd/mtd.yaml | 2 +- arch/arm/mach-omap1/board-ams-delta.c | 8 +- arch/mips/boot/dts/ni/169445.dts | 13 +- drivers/mtd/nand/raw/Makefile | 2 +- drivers/mtd/nand/raw/ams-delta.c | 60 ++++---- drivers/mtd/nand/raw/{gpio.c => nand-gpio.c} | 120 +++++---------- 8 files changed, 251 insertions(+), 169 deletions(-) --- base-commit: be3ca57cfb777ad820c6659d52e60bbdd36bf5ff change-id: 20231105-fix-mips-nand-c91ebd80fa4f Best regards,