[GIT,PULL,5/7] Renesas RISC-V defconfig updates for v6.2

Message ID	cover.1668788928.git.geert+renesas@glider.be
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Headers	show Return-Path: <linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org> From: Geert Uytterhoeven <geert+renesas@glider.be> To: arm-soc <arm@kernel.org>, soc <soc@kernel.org> Cc: Magnus Damm <magnus.damm@gmail.com>, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven <geert+renesas@glider.be> Subject: [GIT PULL 5/7] Renesas RISC-V defconfig updates for v6.2 Date: Fri, 18 Nov 2022 17:45:02 +0100 Message-Id: <cover.1668788928.git.geert+renesas@glider.be> In-Reply-To: <cover.1668788918.git.geert+renesas@glider.be> References: <cover.1668788918.git.geert+renesas@glider.be> MIME-Version: 1.0 preview: The following changes since commit 9abf2313adc1ca1b6180c508c25f22f9395cc780: Linux 6.1-rc1 (2022-10-16 15:36:24 -0700) are available in the Git repository at: Content analysis details: (-0.4 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [2a02:1800:120:4:0:0:f00:14 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 SPF_NONE SPF: sender does not publish an SPF Record 0.2 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org
Series	Renesas SoC updates for v6.2 (take two) \| expand [GIT,PULL,0/7] Renesas SoC updates for v6.2 (take two) [GIT,PULL,1/7] Renesas ARM defconfig updates for v6.2 [GIT,PULL,2/7] Renesas ARM DT updates for v6.2 (take two) [GIT,PULL,3/7] Renesas driver updates for v6.2 (take two) [GIT,PULL,4/7] Renesas DT binding updates for v6.2 (take two) [GIT,PULL,5/7] Renesas RISC-V defconfig updates for v6.2 [GIT,PULL,6/7] Renesas RISC-V DT updates for v6.2 [GIT,PULL,7/7] Renesas RISC-V SoC updates for v6.2

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cover.1668788928.git.geert+renesas@glider.be

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From: Geert Uytterhoeven <geert+renesas@glider.be>
To: arm-soc <arm@kernel.org>,
	soc <soc@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-renesas-soc@vger.kernel.org,
	Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [GIT PULL 5/7] Renesas RISC-V defconfig updates for v6.2
Date: Fri, 18 Nov 2022 17:45:02 +0100
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Series

Renesas SoC updates for v6.2 (take two) | expand

Message

Geert Uytterhoeven Nov. 18, 2022, 4:45 p.m. UTC

The following changes since commit 9abf2313adc1ca1b6180c508c25f22f9395cc780:

  Linux 6.1-rc1 (2022-10-16 15:36:24 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git tags/renesas-riscv-defconfig-for-v6.2-tag1

for you to fetch changes up to 1776fca7fadbac2260a22e2ecb708e8a1ba9310d:

  riscv: configs: defconfig: Enable Renesas RZ/Five SoC (2022-11-10 16:37:58 +0100)

----------------------------------------------------------------
Renesas RISC-V defconfig updates for v6.2

  - Enable support for the Renesas RZ/Five SoC and the RZ/Five SMARC EVK
    board in the risc-v defconfig.

----------------------------------------------------------------
Lad Prabhakar (1):
      riscv: configs: defconfig: Enable Renesas RZ/Five SoC

 arch/riscv/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

[GIT,PULL,5/7] Renesas RISC-V defconfig updates for v6.2

Pull-request

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