From patchwork Tue Jul 12 18:32:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 647561 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rprH84mzBz9s8d for ; Wed, 13 Jul 2016 04:35:00 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=yNPpzhBE; dkim-atps=neutral Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bN2Uh-0000mp-UP; Tue, 12 Jul 2016 18:33:19 +0000 Received: from mail-vk0-x230.google.com ([2607:f8b0:400c:c05::230]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bN2Ue-0000lA-PJ for linux-arm-kernel@lists.infradead.org; Tue, 12 Jul 2016 18:33:17 +0000 Received: by mail-vk0-x230.google.com with SMTP id f7so34170109vkb.3 for ; Tue, 12 Jul 2016 11:32:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=FfDIXSCERZp4VOk8bbB3z6gfscZDgNOMlpK8WPww6go=; b=yNPpzhBEQjp8utMqA2X6KCrSUdHOr8nda435LyFYmtveg/K8k9Fb9lf1ongIbQ1W8c XO0uVnCzP/r1rbrxrxb9d2iedM9aeQABUlOCsB8AqmPvqC/MMepPWYoEBHAxqqJtiVsH Vzfv+iBdKei10QMwJc3noOAmIJo8USKPnWKxNL/TcOvFovHsQDRD7xL79yOt1+uLSMvs 07H/GnjId0g22cWkzwiWPkHrB7jNh093mXjv4PLvRj+VBqJEGIme2xzMNeGBXO027FXx TEkp8bmwp0cj6f1IFuXmLgazNV3MDnGx4QAhunElr1cpHE/inquLOu6A1GY/Y0bOH1HA EuZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=FfDIXSCERZp4VOk8bbB3z6gfscZDgNOMlpK8WPww6go=; b=SjiDmwQTed9xiph7EQuOznIYAdc5FWJoZ5i/cWSsOL1hCsbBAg3vYRmEYlk/hgB96B YX4kKg0dwn/s9iaqJapQoAZpKu+qYDdGA0MYOGTOnbyzpUwu2Q2f/F1i89ask9fOO6ZN NAozYo9yqZHNX9dUL+cNwepKD4GwrKUQGIjviOHt+Aja1VBzrq3YvtjWYwv9SJSgqDS4 Ti9RIVgCiJ+83uB5abRjGdAkEznJUjAcgBYX3wCuHPHgS7/KIhM/YnntzJ5do/J0DoX/ fptRimOXVwV1t4bUBv77ZXyNchC43zxCxpE0EYlJSgpxX8leLnapT3MU6cNoNNuu0fPT wR0A== X-Gm-Message-State: ALyK8tJjDyH9IviBsp+pX/KaPIF8gjuehTUPG7Vjc9lrFcZWfPFQueS1uj/Lqlbhy6HHNTVDCCSugbLbcFEISQ== X-Received: by 10.176.6.131 with SMTP id g3mr1841454uag.29.1468348375012; Tue, 12 Jul 2016 11:32:55 -0700 (PDT) MIME-Version: 1.0 Received: by 10.31.92.81 with HTTP; Tue, 12 Jul 2016 11:32:54 -0700 (PDT) In-Reply-To: References: <1468145266-7567-1-git-send-email-uwe@kleine-koenig.org> <1468145266-7567-4-git-send-email-uwe@kleine-koenig.org> <20160711073721.GM16643@pengutronix.de> <20160712073859.GQ16643@pengutronix.de> From: Fabio Estevam Date: Tue, 12 Jul 2016 15:32:54 -0300 Message-ID: Subject: Re: [PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value To: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160712_113317_003053_C3583020 X-CRM114-Status: GOOD ( 15.77 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2607:f8b0:400c:c05:0:0:0:230 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (festevam[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Uwe_Kleine=2DK=C3=B6nig?= , Shawn Guo , "linux-arm-kernel@lists.infradead.org" , Sascha Hauer Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Hi Uwe, On Tue, Jul 12, 2016 at 12:15 PM, Fabio Estevam wrote: > I will try to get access to a mx25pdk and will confirm soon. Thanks Please find attached the patch after reading all the PAD_CTL registers. Feel free to submit it as part of your series. From a2b9e24841909868803576c68c2d2b064a00d4a9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 12 Jul 2016 15:19:02 -0300 Subject: [PATCH] ARM: dts: imx25-pdk: Explicitly setup PAD config in dts When passing 0x80000000 as the PAD_CTL config value, the kernel does not touch the PAD_CTL egisters and use the value that comes from the bootloader. Instead of relying on the bootloader it is better to have the kernel to explicitly configure the PAD_CTL registers. Modified each 0x80000000 occurrance by reading the real PAD_CTL registers values in the bootloader and putting in the dts. Also tested by booting the resulting dtb. Signed-off-by: Fabio Estevam --- arch/arm/boot/dts/imx25-pdk.dts | 58 ++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts index 7029210..e997e2b 100644 --- a/arch/arm/boot/dts/imx25-pdk.dts +++ b/arch/arm/boot/dts/imx25-pdk.dts @@ -159,56 +159,56 @@ fsl,pins = < MX25_PAD_GPIO_A__CAN1_TX 0x0 MX25_PAD_GPIO_B__CAN1_RX 0x0 - MX25_PAD_D14__GPIO_4_6 0x80000000 + MX25_PAD_D14__GPIO_4_6 0xa1 >; }; pinctrl_esdhc1: esdhc1grp { fsl,pins = < - MX25_PAD_SD1_CMD__SD1_CMD 0x80000000 - MX25_PAD_SD1_CLK__SD1_CLK 0x80000000 - MX25_PAD_SD1_DATA0__SD1_DATA0 0x80000000 - MX25_PAD_SD1_DATA1__SD1_DATA1 0x80000000 - MX25_PAD_SD1_DATA2__SD1_DATA2 0x80000000 - MX25_PAD_SD1_DATA3__SD1_DATA3 0x80000000 - MX25_PAD_A14__GPIO_2_0 0x80000000 - MX25_PAD_A15__GPIO_2_1 0x80000000 + MX25_PAD_SD1_CMD__SD1_CMD 0xe1 + MX25_PAD_SD1_CLK__SD1_CLK 0xd1 + MX25_PAD_SD1_DATA0__SD1_DATA0 0xe1 + MX25_PAD_SD1_DATA1__SD1_DATA1 0xd1 + MX25_PAD_SD1_DATA2__SD1_DATA2 0xd1 + MX25_PAD_SD1_DATA3__SD1_DATA3 0xe1 + MX25_PAD_A14__GPIO_2_0 0x80 + MX25_PAD_A15__GPIO_2_1 0x00 >; }; pinctrl_fec: fecgrp { fsl,pins = < - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDC__FEC_MDC 0x00 MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x00 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x00 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x00 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0xc0 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0xc0 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0xc0 MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - MX25_PAD_A17__GPIO_2_3 0x80000000 - MX25_PAD_D12__GPIO_4_8 0x80000000 + MX25_PAD_A17__GPIO_2_3 0x00 + MX25_PAD_D12__GPIO_4_8 0x00 >; }; pinctrl_i2c1: i2c1grp { fsl,pins = < - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 + MX25_PAD_I2C1_CLK__I2C1_CLK 0xa8 + MX25_PAD_I2C1_DAT__I2C1_DAT 0xa8 >; }; pinctrl_kpp: kppgrp { fsl,pins = < - MX25_PAD_KPP_ROW0__KPP_ROW0 0x80000000 - MX25_PAD_KPP_ROW1__KPP_ROW1 0x80000000 - MX25_PAD_KPP_ROW2__KPP_ROW2 0x80000000 - MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000 - MX25_PAD_KPP_COL0__KPP_COL0 0x80000000 - MX25_PAD_KPP_COL1__KPP_COL1 0x80000000 - MX25_PAD_KPP_COL2__KPP_COL2 0x80000000 - MX25_PAD_KPP_COL3__KPP_COL3 0x80000000 + MX25_PAD_KPP_ROW0__KPP_ROW0 0xa0 + MX25_PAD_KPP_ROW1__KPP_ROW1 0xa0 + MX25_PAD_KPP_ROW2__KPP_ROW2 0xe0 + MX25_PAD_KPP_ROW3__KPP_ROW3 0xe0 + MX25_PAD_KPP_COL0__KPP_COL0 0xa8 + MX25_PAD_KPP_COL1__KPP_COL1 0xa8 + MX25_PAD_KPP_COL2__KPP_COL2 0xa8 + MX25_PAD_KPP_COL3__KPP_COL3 0xa8 >; }; @@ -244,7 +244,7 @@ fsl,pins = < MX25_PAD_UART1_RTS__UART1_RTS 0xe0 MX25_PAD_UART1_CTS__UART1_CTS 0xe0 - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_TXD__UART1_TXD 0x00 MX25_PAD_UART1_RXD__UART1_RXD 0xc0 >; }; -- 1.9.1