From patchwork Thu Jun 25 21:29:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 488560 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4E45D140273 for ; Fri, 26 Jun 2015 07:32:14 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=D5R+uBLw; dkim-atps=neutral Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z8EiL-00048a-V5; Thu, 25 Jun 2015 21:29:41 +0000 Received: from mail-la0-x234.google.com ([2a00:1450:4010:c03::234]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z8EiI-00046u-5W for linux-arm-kernel@lists.infradead.org; Thu, 25 Jun 2015 21:29:38 +0000 Received: by lagi2 with SMTP id i2so52909583lag.2 for ; Thu, 25 Jun 2015 14:29:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=Ps08GM4c+XTKS8Nd2vLGIxTRosH/7CtrrPi9SaUN7r4=; b=D5R+uBLwqI1TT+cwgUgYao2MIYlEfbfh/+a6MipqAxuFHZvg60++atyYWytrRKPbP3 Ca0kit0L9WrQgBrKEyxNXn7SUUolUYsxferOAE2W3eDPhgKNHQjSH7jETakasLXz0Wa0 kssqULc8vjdvEUSUiafUoCSMr34Swz7kU2mOUNEOriRN0lni5YYjCjQjNpTNMmcTK3i3 mgk0R0MrzG8oG6nhwr6ezNA/LZS2WllFQ7NJ42j7ZMY++UEINzY5IxXaKwNBjbR100vP OpByk1tdEi77hz2l9baXX1w2aL9yudRM48tXFzpuW9IKpWZkxb/9xT6Qi1zXtAfqSWXD 9qLw== MIME-Version: 1.0 X-Received: by 10.152.19.8 with SMTP id a8mr46688683lae.121.1435267753809; Thu, 25 Jun 2015 14:29:13 -0700 (PDT) Received: by 10.152.148.129 with HTTP; Thu, 25 Jun 2015 14:29:13 -0700 (PDT) In-Reply-To: References: <20150624172900.GN7557@n2100.arm.linux.org.uk> Date: Thu, 25 Jun 2015 18:29:13 -0300 Message-ID: Subject: Re: L2 Cache enable on i.MX5 From: Fabio Estevam To: Robert Daniels X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150625_142938_386314_EFC209D3 X-CRM114-Status: GOOD ( 16.36 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [2a00:1450:4010:c03:0:0:0:234 listed in] [list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (festevam[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain Cc: Russell King - ARM Linux , "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org On Wed, Jun 24, 2015 at 7:53 PM, Robert Daniels wrote: > I see - so the boot loader is not supposed to enable the L2 cache and it should > not be enabled until after the decompressor runs. > > In that case, where should the kernel be enabling the L2 cache? I'm using the > 3.14 kernel for this i.MX53 product and the L2 cache is definitely not enabled. > > I see that there is a imx_init_l2cache defined which is being called by the imx6 > and imx35 platform code but it is not being called for the i.mx5... should it? Should we enable the L2 cache like it is done in Barebox? Regards, Fabio Estevam --- a/arch/arm/mach-imx/mach-imx53.c +++ b/arch/arm/mach-imx/mach-imx53.c @@ -25,7 +25,13 @@ static void __init imx53_init_early(void) { + unsigned int r; + mxc_set_cpu_type(MXC_CPU_MX53); + + __asm__ __volatile__("mrc 15, 0, %0, c1, c0, 1":"=r"(r)); + r |= 1 << 1; /* enable L2 cache */ + __asm__ __volatile__("mcr 15, 0, %0, c1, c0, 1" : : "r"(r)); } static void __init imx53_dt_init(void)