From patchwork Thu Dec 22 02:50:58 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Eric Miao X-Patchwork-Id: 132768 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 04E47B7143 for ; Thu, 22 Dec 2011 13:54:19 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1RdYkg-0003Nr-EZ; Thu, 22 Dec 2011 02:51:26 +0000 Received: from mail-vw0-f49.google.com ([209.85.212.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RdYkb-0003NN-GZ for linux-arm-kernel@lists.infradead.org; Thu, 22 Dec 2011 02:51:23 +0000 Received: by vbbfs19 with SMTP id fs19so8578203vbb.36 for ; Wed, 21 Dec 2011 18:51:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:from:date :x-google-sender-auth:message-id:subject:to:cc:content-type :content-transfer-encoding; bh=EHMb/UxOstJom2JkHDSshfUlLx3k4OvU+6GiyouGqsQ=; b=iW/5liyncDFTH7jIOzD66BMbGtOw2rxmnTbdsCMQ8eBz0RsvNpSl6TL9kXSstBUmjn wZs8nK6CK1ptxPNf73QbWe5aWvmf/q43Ry59GeasCRDxPQLGZ0A7FdkXVlUdhdaksNJf ZPM/soV2u7w5IhMLYAL3dPcG7HDYfBXaF6RCg= Received: by 10.52.94.97 with SMTP id db1mr5362776vdb.16.1324522279231; Wed, 21 Dec 2011 18:51:19 -0800 (PST) MIME-Version: 1.0 Received: by 10.52.110.99 with HTTP; Wed, 21 Dec 2011 18:50:58 -0800 (PST) In-Reply-To: <20111221153327.GB6470@S2100-06.ap.freescale.net> References: <1324478303-3899-1-git-send-email-eric.miao@linaro.org> <20209.62098.146087.510816@ipc1.ka-ro> <20111221152345.GA6470@S2100-06.ap.freescale.net> <20111221153327.GB6470@S2100-06.ap.freescale.net> From: Eric Miao Date: Thu, 22 Dec 2011 10:50:58 +0800 X-Google-Sender-Auth: xy0cA4Ra3uoqYklutef1Y0w7gGM Message-ID: Subject: Re: [PATCH] ARM: imx6q: build pm code only when CONFIG_PM selected To: Shawn Guo X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (eric.y.miao[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Shawn Guo , linux-arm-kernel , =?UTF-8?Q?Lothar_Wa=C3=9Fmann?= X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org On Wed, Dec 21, 2011 at 11:33 PM, Shawn Guo wrote: > On Wed, Dec 21, 2011 at 11:23:47PM +0800, Shawn Guo wrote: >> > diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S >> > index 6229efb..830b5c8 100644 >> > --- a/arch/arm/mach-imx/head-v7.S >> > +++ b/arch/arm/mach-imx/head-v7.S >> > @@ -80,12 +80,14 @@ ENDPROC(v7_secondary_startup) >> >     .align >> > >> >     .macro  pl310_resume >> > +#ifdef CONFIG_CACHE_L2X0 >> >     ldr     r2, phys_l2x0_saved_regs >> >     ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0 >> >     ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value >> >     str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl >> >     mov     r1, #0x1 >> >     str     r1, [r0, #L2X0_CTRL]            @ re-enable L2 >> > +#endif >> >     .endm >> > >> >  ENTRY(v7_cpu_resume) >> > @@ -94,6 +96,8 @@ ENTRY(v7_cpu_resume) >> >     b       cpu_resume >> >  ENDPROC(v7_cpu_resume) >> > >> > +#ifdef CONFIG_CACHE_L2X0 >> >     .globl  phys_l2x0_saved_regs >> >  phys_l2x0_saved_regs: >> >          .long   0 >> > +#endif >> >> But I'm thinking about if we can solve this at L2X0 level instead of >> introducing ifdef all over every platform code. >> > Never mind.  Even if we have L2X0_R_PHY_BASE L2X0_R_AUX_CTRL defined > for non-L2X0 build, we still need ifdef for pl310_resume calling. > > But can we save one ifdef by leaving phys_l2x0_saved_regs there? Or we can have something like this: diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S index a59cae7..cec23a8 100644 --- a/arch/arm/mach-imx/head-v7.S +++ b/arch/arm/mach-imx/head-v7.S @@ -80,6 +80,7 @@ ENDPROC(v7_secondary_startup) .data .align +#ifdef CONFIG_CACHE_L2X0 .macro pl310_resume ldr r2, phys_l2x0_saved_regs ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 @@ -89,13 +90,17 @@ ENDPROC(v7_secondary_startup) str r1, [r0, #L2X0_CTRL] @ re-enable L2 .endm + .globl phys_l2x0_saved_regs +phys_l2x0_saved_regs: + .long 0 +#else + .macro pl310_resume + .endm +#endif + ENTRY(v7_cpu_resume) bl v7_invalidate_l1 pl310_resume b cpu_resume ENDPROC(v7_cpu_resume) - - .globl phys_l2x0_saved_regs -phys_l2x0_saved_regs: - .long 0 #endif