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Received: from rere.qmqm.pl ([91.227.64.183]) by merlin.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gLaOo-0008Pm-RU for linux-arm-kernel@lists.infradead.org; Sat, 10 Nov 2018 21:02:36 +0000 Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 42sqFH3B3NzSP; Sat, 10 Nov 2018 22:01:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1541883683; bh=WebcDRCIJFy5WNQCoErpH9NzmoM8uF/zKeqyHpZVuS0=; h=Date:In-Reply-To:References:From:Subject:To:Cc:From; b=dApjIhB0R97WKHMbSWxvDhrJMFYwTPFkPegYxrcI9UiL5Tkeb8Nd7G8F0c8n4wbK3 ahgQAgB7lYgwr8MgNB+SCHRxqUHPQT/6qPKFzVPTBeRH3AAm8YWGgwapCAuEMpmYWC +h+uC7oQFu1ohA3KLlouxtmLSonik6UP/pnDUEmaG6ja40j8U7rMfriIYfbHvpTSmH i+Mi5ItyAlvYsRrxUcKqIDOw83n3Xe9Sw+NTPzaoXxShiu2VEdrc5uKpDuQ4YlJ+sn qAlbsMwfOg/bCynkbCxuCeCk427PeVu+fCMjmfetn9vYsHz82WfpaK2H0yR1vE4T3l aIebc5kB5gHag== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.100.2 at mail Date: Sat, 10 Nov 2018 22:02:22 +0100 Message-Id: <7124870dfcabaea33ca3d7623714887f65654646.1541882833.git.mirq-linux@rere.qmqm.pl> In-Reply-To: References: From: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Subject: [PATCH 2/3] ARM: trusted_foundations: enable L2x0 cache via firmware_ops MIME-Version: 1.0 To: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181110_160235_238107_BF217C68 X-CRM114-Status: GOOD ( 14.75 ) X-Spam-Score: -0.1 (/) X-Spam-Report: SpamAssassin version 3.4.2 on merlin.infradead.org summary: Content analysis details: (-0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, Mark Rutland , Dmitry Osipenko , Russell King Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Use firmware_ops to provide hook for cache initialization through Trusted Foundations firmware, as some writes need Secure mode. Avoid l2x0_base conflict (duplication) with PMU driver by sharing l2x0_name and using l2x0_name as the enable flag there. Signed-off-by: Michał Mirosław --- arch/arm/firmware/trusted_foundations.c | 46 +++++++++++++++++++++++++ arch/arm/mm/cache-l2x0.c | 8 +++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 689e6565abfc..135068119453 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -17,11 +17,19 @@ #include #include #include +#include #include +#include +#include #include +#define TF_CACHE_MAINT 0xfffff100 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 +#define TF_CACHE_INIT 1 +#define TF_CACHE_FLUSH 2 +#define TF_CACHE_REENABLE 4 + #define TF_CPU_PM 0xfffffffc #define TF_CPU_PM_S3 0xffffffe3 #define TF_CPU_PM_S2 0xffffffe6 @@ -67,9 +75,47 @@ static int tf_prepare_idle(void) return 0; } +#ifdef CONFIG_CACHE_L2X0 +static void tf_write_sec(unsigned long val, unsigned reg) +{ + unsigned long cur = readl_relaxed(l2x0_base + reg); + + pr_warn("TF: ignoring write_sec[0x%x]: 0x%08lx -> 0x%08lx\n", reg, cur, val); +} + +static void tf_disable_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_FLUSH, l2x0_way_mask); +} + +static void tf_resume_cache(void) +{ + unsigned long aux_val = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_REENABLE, aux_val); +} + +static void tf_configure_cache(const struct l2x0_regs *regs) +{ + outer_cache.disable = tf_disable_cache; + outer_cache.resume = tf_resume_cache; +} + +static int tf_init_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_INIT, 0); + + outer_cache.write_sec = tf_write_sec; + outer_cache.configure = tf_configure_cache; + return 0; +} +#endif /* CONFIG_CACHE_L2X0 */ + static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, .prepare_idle = tf_prepare_idle, +#ifdef CONFIG_CACHE_L2X0 + .l2x0_init = tf_init_cache, +#endif }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 2b6a023fea3f..f1268e9b35f0 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "cache-tauros3.h" #include "cache-aurora-l2.h" @@ -37,6 +38,7 @@ struct l2c_init_data { const char *type; unsigned way_size_0; unsigned num_lock; + void (*init)(void __iomem *, u32 *, u32 *); void (*of_parse)(const struct device_node *, u32 *, u32 *); void (*enable)(void __iomem *, unsigned); void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); @@ -1760,6 +1762,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) u32 cache_id; u32 cache_level = 2; bool nosync = false; + int err; np = of_find_matching_node(NULL, l2x0_ids); if (!np) @@ -1792,6 +1795,11 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) nosync = of_property_read_bool(np, "arm,outer-sync-disable"); + /* Call firmware init */ + err = call_firmware_op(l2x0_init); + if (err && err != -ENOSYS) + return err; + /* Read back current (default) hardware configuration */ if (data->save) data->save(l2x0_base);