mbox

[GIT,PULL,v2] STi SoC changes for v4.8

Message ID 577E01B5.2030206@st.com
State New
Headers show

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git

Message

Patrice CHOTARD July 7, 2016, 7:16 a.m. UTC
The following changes since commit 4c2e07c6a29e0129e975727b9f57eede813eea85:

   Linux 4.7-rc5 (2016-06-26 17:52:03 -0700)

are available in the git repository at:

   git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti.git 
tags/sti-soc-for-v4.8

for you to fetch changes up to 55aa35180c57d82f3db23e5aabce97acb0d36681:

   ARM: sti: Implement dummy L2 cache's write_sec (2016-07-01 16:23:44 
+0200)

----------------------------------------------------------------

Highlights:
-----------
- Add a dummy L2 cache's write_sec callback as in non secure mode execution,
   we can't get access to L2 cache secure registers
- Cosmetics change, in case of dump_stack, update the hardware name with a
   more generic for the STi SoCs family

----------------------------------------------------------------
Patrice Chotard (1):
       ARM: sti: Implement dummy L2 cache's write_sec

Peter Griffin (1):
       ARM: STi: Update machine _namestr to be more generic.

  arch/arm/mach-sti/board-dt.c | 11 ++++++++++-
  1 file changed, 10 insertions(+), 1 deletion(-)

Comments

Arnd Bergmann July 7, 2016, 1:23 p.m. UTC | #1
On Thursday, July 7, 2016 9:16:05 AM CEST Patrice Chotard wrote:
> Highlights:
> -----------
> - Add a dummy L2 cache's write_sec callback as in non secure mode execution,
>    we can't get access to L2 cache secure registers
> - Cosmetics change, in case of dump_stack, update the hardware name with a
>    more generic for the STi SoCs family
> 

This is also based on -rc5, please send a third version rebased to -rc3 or
earlier.

	Arnd
Patrice CHOTARD July 11, 2016, 7:38 a.m. UTC | #2
On 07/07/2016 03:23 PM, Arnd Bergmann wrote:
> On Thursday, July 7, 2016 9:16:05 AM CEST Patrice Chotard wrote:
>> Highlights:
>> -----------
>> - Add a dummy L2 cache's write_sec callback as in non secure mode execution,
>>     we can't get access to L2 cache secure registers
>> - Cosmetics change, in case of dump_stack, update the hardware name with a
>>     more generic for the STi SoCs family
>>
> This is also based on -rc5, please send a third version rebased to -rc3 or
> earlier.

Hi Arnd

V3 will be send shortly

Thanks

Patrice

>
> 	Arnd