@@ -44,9 +44,9 @@
#define MX25_CCM_LPIMR0 0x68
#define MX25_CCM_LPIMR1 0x6C
-static void __iomem *avic_base;
-static void __iomem *mx25_ccm_base;
-static struct irq_domain *domain;
+static void __iomem *avic_base __ro_after_init;
+static void __iomem *mx25_ccm_base __ro_after_init;
+static struct irq_domain *domain __ro_after_init;
#ifdef CONFIG_FIQ
static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type)
@@ -27,7 +27,7 @@
#define IMR_NUM 4
#define GPC_MAX_IRQS (IMR_NUM * 32)
-static void __iomem *gpc_base;
+static void __iomem *gpc_base __ro_after_init;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];
@@ -18,7 +18,7 @@
#include "hardware.h"
u32 g_diag_reg;
-static void __iomem *scu_base;
+static void __iomem *scu_base __ro_after_init;
static struct map_desc scu_io_desc __initdata = {
/* .virtual and .pfn are run-time assigned */
@@ -130,11 +130,11 @@ struct imx5_cpu_suspend_info {
struct imx5_suspend_io_state io_state[MX5_MAX_SUSPEND_IOSTATE];
} __aligned(8);
-static void __iomem *ccm_base;
-static void __iomem *cortex_base;
-static void __iomem *gpc_base;
-static void __iomem *suspend_ocram_base;
-static void (*imx5_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
+static void __iomem *ccm_base __ro_after_init;
+static void __iomem *cortex_base __ro_after_init;
+static void __iomem *gpc_base __ro_after_init;
+static void __iomem *suspend_ocram_base __ro_after_init;
+static void (*imx5_suspend_in_ocram_fn)(void __iomem *ocram_vbase) __ro_after_init;
/*
* set cpu low power mode before WFI instruction. This function is called
@@ -60,9 +60,9 @@
#define MX6Q_SUSPEND_OCRAM_SIZE 0x1000
#define MX6_MAX_MMDC_IO_NUM 33
-static void __iomem *ccm_base;
-static void __iomem *suspend_ocram_base;
-static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
+static void __iomem *ccm_base __ro_after_init;
+static void __iomem *suspend_ocram_base __ro_after_init;
+static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase) __ro_after_init;
/*
* suspend ocram space layout:
@@ -25,7 +25,7 @@
#define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM)
#define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM)
-static void __iomem *smc1_base;
+static void __iomem *smc1_base __ro_after_init;
int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode)
{
@@ -36,10 +36,10 @@
#define GPC_PGC_C1 0x840
#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
-static void __iomem *src_base;
+static void __iomem *src_base __ro_after_init;
static DEFINE_SPINLOCK(scr_lock);
-static bool gpr_v2;
-static void __iomem *gpc_base;
+static bool gpr_v2 __ro_after_init;
+static void __iomem *gpc_base __ro_after_init;
static const int sw_reset_bits[5] = {
BP_SRC_SCR_SW_GPU_RST,
@@ -23,9 +23,9 @@
#include "common.h"
#include "hardware.h"
-static void __iomem *wdog_base;
-static struct clk *wdog_clk;
-static int wcr_enable = (1 << 2);
+static void __iomem *wdog_base __ro_after_init;
+static struct clk *wdog_clk __ro_after_init;
+static int wcr_enable __ro_after_init = (1 << 2);
/*
* Reset the system. It is called by machine_restart().
@@ -43,8 +43,8 @@
#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
-static void __iomem *tzic_base;
-static struct irq_domain *domain;
+static void __iomem *tzic_base __ro_after_init;
+static struct irq_domain *domain __ro_after_init;
#define TZIC_NUM_IRQS 128