| Message ID | 20190211141333.28725-4-u.kleine-koenig@pengutronix.de |
|---|---|
| State | New |
| Headers | show |
| Series | [01/15] ARM: dts: imx6qdl-fdi-fs700-m60: Use explicit swpad values | expand |
Hi Uwe, On 19-02-11 15:13, Uwe Kleine-König wrote: > Instead of relying on reset defaults or a bootloader to configure > use explicit values for the swpad configuration. Here the reset > defaults of the i.MX6dl are used owing to lack of other evidence. (They > differ from the i.MX6q defaults for GPIO_0 and KEY_ROW4.) Rely on the reset/bootloader values isn't that good at all. Since the bootloader use case can be different. I've checked your patch against a vanilla barebox (bootloader) which includes this devicetree. My test setup was a imx6q pfla02 SoM and a pbab01 baseboard. Please look my comment below. > > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> > --- > arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi > index 1b50b01e9bac..8e04ab7df2d7 100644 > --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi > +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi > @@ -211,11 +211,11 @@ > imx6q-phytec-pfla02 { > pinctrl_hog: hoggrp { > fsl,pins = < > - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 > - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ > - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */ > - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ > - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ > + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 > + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 /* SPI NOR chipselect */ > + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* PMIC interrupt */ > + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* Green LED */ > + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* Red LED */ Don't wanna nitpick, the MX6QDL_PAD_EIM_EB3__GPIO2_IO31 pad should be configured to 0x1b0b0 too, but I don't know the default imx6dl behaviour as you mentioned above. So I'm fine with the patch. Acked-by: Marco Felsch <m.felsch@pengutronix.de> > >; > }; > > @@ -299,7 +299,7 @@ > }; > > pinctrl_pcie: pciegrp { > - fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>; > + fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0>; > }; > > pinctrl_uart3: uart3grp { > @@ -320,7 +320,7 @@ > > pinctrl_usbh1: usbh1grp { > fsl,pins = < > - MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 > + MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0 > >; > }; > > @@ -328,7 +328,7 @@ > fsl,pins = < > MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 > MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 > - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 > + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 > >; > }; > > @@ -356,8 +356,8 @@ > > pinctrl_usdhc3_cdwp: usdhc3cdwp { > fsl,pins = < > - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 > - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 > + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 > + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 > >; > }; > > -- > 2.20.1 > > >
On Tue, Feb 12, 2019 at 09:15:45AM +0100, Marco Felsch wrote: > Hi Uwe, > > On 19-02-11 15:13, Uwe Kleine-König wrote: > > Instead of relying on reset defaults or a bootloader to configure > > use explicit values for the swpad configuration. Here the reset > > defaults of the i.MX6dl are used owing to lack of other evidence. (They > > differ from the i.MX6q defaults for GPIO_0 and KEY_ROW4.) > > Rely on the reset/bootloader values isn't that good at all. Since the > bootloader use case can be different. I've checked your patch against a > vanilla barebox (bootloader) which includes this devicetree. My test > setup was a imx6q pfla02 SoM and a pbab01 baseboard. Please look my > comment below. > > > > > Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> > > --- > > arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 20 ++++++++++---------- > > 1 file changed, 10 insertions(+), 10 deletions(-) > > > > diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi > > index 1b50b01e9bac..8e04ab7df2d7 100644 > > --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi > > +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi > > @@ -211,11 +211,11 @@ > > imx6q-phytec-pfla02 { > > pinctrl_hog: hoggrp { > > fsl,pins = < > > - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 > > - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ > > - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */ > > - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ > > - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ > > + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 > > + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 /* SPI NOR chipselect */ > > + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* PMIC interrupt */ > > + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* Green LED */ > > + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* Red LED */ > > Don't wanna nitpick, the MX6QDL_PAD_EIM_EB3__GPIO2_IO31 pad should be > configured to 0x1b0b0 too, but I don't know the default imx6dl > behaviour as you mentioned above. So I'm fine with the patch. This is a bug in my linter's data table. EIM_EB3 should use 0x1b0b0 on both imx6q and imx6dl. I will wait a bit more for feedback, and then probably respin with this fixed. Thanks for your input. Best regards Uwe
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 1b50b01e9bac..8e04ab7df2d7 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -211,11 +211,11 @@ imx6q-phytec-pfla02 { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 - MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0 /* SPI NOR chipselect */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* PMIC interrupt */ + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* Green LED */ + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* Red LED */ >; }; @@ -299,7 +299,7 @@ }; pinctrl_pcie: pciegrp { - fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>; + fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b0>; }; pinctrl_uart3: uart3grp { @@ -320,7 +320,7 @@ pinctrl_usbh1: usbh1grp { fsl,pins = < - MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000 + MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0 >; }; @@ -328,7 +328,7 @@ fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 >; }; @@ -356,8 +356,8 @@ pinctrl_usdhc3_cdwp: usdhc3cdwp { fsl,pins = < - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 >; };
Instead of relying on reset defaults or a bootloader to configure use explicit values for the swpad configuration. Here the reset defaults of the i.MX6dl are used owing to lack of other evidence. (They differ from the i.MX6q defaults for GPIO_0 and KEY_ROW4.) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)