From patchwork Fri Jul 1 10:10:19 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Catalin Marinas X-Patchwork-Id: 102891 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3C50AB6F67 for ; Fri, 1 Jul 2011 20:11:04 +1000 (EST) Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QcagY-00087D-Uq; Fri, 01 Jul 2011 10:10:55 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QcagK-0003pV-FD; Fri, 01 Jul 2011 10:10:40 +0000 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QcagE-0003oy-L4 for linux-arm-kernel@lists.infradead.org; Fri, 01 Jul 2011 10:10:38 +0000 Received: from e102109-lin.cambridge.arm.com (e102109-lin.cambridge.arm.com [10.1.77.45]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id p61A7jY3011442; Fri, 1 Jul 2011 11:07:45 +0100 (BST) Date: Fri, 1 Jul 2011 11:10:19 +0100 From: Catalin Marinas To: heechul Yun Subject: Re: Unnecessary cache-line flush on page table updates ? Message-ID: <20110701101019.GA1723@e102109-lin.cambridge.arm.com> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-06-14) X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110701_061034_954226_964C9037 X-CRM114-Status: GOOD ( 20.37 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: "linux-arm-kernel@lists.infradead.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org On Fri, Jul 01, 2011 at 08:04:42AM +0100, heechul Yun wrote: > Based on TRM of Cortex A9, the MMU reads page table entries from L1-D > cache not from memory. Then I think we do not need to flush the cache > line in the following code because MMU will always see up-to-date view > of page table in both UP and SMP systems. > > linux/arch/arm/mm/proc-v7.S > > ENTRY(cpu_v7_set_pte_ext) > ... > mcr p15, 0, r0, c7, c10, 1 @ flush_pte from > D-cache // why we need this in A9? > … > > If this is a necessary one, could you please explain the reason? Thanks. No, it's not necessary, only that this file is used by other processors as well. The solution below checks the ID_MMFR3[23:20] bits (coherent walk) and avoid flushing if the value is 1. The same could be done for PMD entries, though that's less critical than the PTEs. Please note that the patch is not fully tested. 8<-------------------- From 67bd5ebdf622637f8293286146441e6292713c3d Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Fri, 1 Jul 2011 10:57:07 +0100 Subject: [PATCH] ARMv7: Do not clean the PTE coherent page table walk is supported This patch adds a check for the ID_MMFR3[23:20] bits (coherent walk) and only cleans the D-cache corresponding to a PTE if coherent page table walks are not supported. Signed-off-by: Catalin Marinas --- arch/arm/mm/proc-v7.S | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 8013afc..fc5b36f 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -166,7 +166,9 @@ ENTRY(cpu_v7_set_pte_ext) ARM( str r3, [r0, #2048]! ) THUMB( add r0, r0, #2048 ) THUMB( str r3, [r0] ) - mcr p15, 0, r0, c7, c10, 1 @ flush_pte + mrc p15, 0, r3, c0, c1, 7 @ read ID_MMFR3 + tst r3, #0xf << 20 @ check the coherent walk bits + mcreq p15, 0, r0, c7, c10, 1 @ flush_pte #endif mov pc, lr ENDPROC(cpu_v7_set_pte_ext)