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(bc-e10-1-11.euhpc.arm.com [10.6.12.88]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9B7F63F487; Mon, 12 Feb 2018 03:20:01 -0800 (PST) From: Vladimir Murzin To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/4] ARM: NOMMU: Reorganise __setup_mpu Date: Mon, 12 Feb 2018 11:19:30 +0000 Message-Id: <1518434373-27907-2-git-send-email-vladimir.murzin@arm.com> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1518434373-27907-1-git-send-email-vladimir.murzin@arm.com> References: <1518434373-27907-1-git-send-email-vladimir.murzin@arm.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [217.140.101.70 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbuild-all@01.org, alexandre.torgue@st.com, linux@armlinux.org.uk, arnd@arndb.de, sza@esh.hu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Currently, we have mixed code placement between .head.text and .text depends on configuration we are building: _text M R(UP) R(SMP) ====================================================== __setup_mpu __HEAD __HEAD text __after_proc_init __HEAD __HEAD text __mmap_switched text text text We are going to support another variant of MPU which is different to PMSAv7 in sense overlapping MPU regions are not allowed, so this patch makes boundaries between these sections precise and consistent: _text M R(UP) R(SMP) ====================================================== __setup_mpu __HEAD __HEAD __HEAD __after_proc_init text text text __mmap_switched text text text Additionally, it paves a path to postpone MPU activation till __after_proc_init where we do set SCTLR anyway and can return directly to __mmap_switched. Tested-by: Szemző András Signed-off-by: Vladimir Murzin --- arch/arm/kernel/head-nommu.S | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index 0d17187..aaa25a6 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -75,8 +75,8 @@ ENTRY(stext) ldr r12, [r10, #PROCINFO_INITFUNC] add r12, r12, r10 ret r12 -1: bl __after_proc_init - b __mmap_switched +1: ldr lr, =__mmap_switched + b __after_proc_init ENDPROC(stext) #ifdef CONFIG_SMP @@ -123,6 +123,7 @@ __secondary_data: /* * Set the Control Register and Read the process ID. */ + .text __after_proc_init: #ifdef CONFIG_CPU_CP15 /* @@ -202,6 +203,7 @@ ENDPROC(__after_proc_init) * * r6: Value to be written to DRSR (and IRSR if required) for PMSAv7_RAM_REGION */ + __HEAD ENTRY(__setup_mpu) @@ -301,6 +303,7 @@ ENDPROC(__setup_pmsa_v7) * r6: pointer at mpu_rgn_info */ + .text ENTRY(__secondary_setup_mpu) /* Use MPU region info supplied by __cpu_up */ ldr r6, [r7] @ get secondary_data.mpu_rgn_info