From patchwork Fri May 22 15:29:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 475689 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 2D323140E33 for ; Sat, 23 May 2015 01:40:28 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yvp0F-0002GD-Qh; Fri, 22 May 2015 15:36:51 +0000 Received: from mail-pd0-f180.google.com ([209.85.192.180]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yvovy-0006Xg-AA for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2015 15:32:27 +0000 Received: by pdbqa5 with SMTP id qa5so22277045pdb.0 for ; Fri, 22 May 2015 08:32:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+0YtSGD6+9/TgTp6owISyn97k1FLQFDkqFOTykaFF0I=; b=SkZ3/WTTLQRh3+QaR77lKAJBjQKRxugS3WjuLHY4jLil0k/dGsNc33TUu1DnfLNjRg 41JXSnwRMAbwuhJJSO4fBV95mzwS0NNx0+q6jAE1GrkguFhNwxqPkPeQW1DBtqmzlmiU IYi3ZHNQ36AS0tn+3pTwee+v3y+psFhBh+GcOeFN6Z3n3pSn20vwZcHp6NHFcCR+SLjw mAZJFjofEEs1osQHCUxVQS7YCrRfLaduQOD60nI3Nn5PgJ9BkUiSNrpAFREt9unhBe1N c9cAqebLvj0hJPYQsFrFR/8fOBw5ytzWs6jG7ZRWd3dEARNYaDJImUrEsR2l29Q0wwC5 UHxA== X-Gm-Message-State: ALoCoQkDNo2a9YkLBeGzylC8Iuz9cwbYLGIiw2zNk0HInd9Pe8so8J2QUeN/gqnld8YhNROTMmxj X-Received: by 10.66.66.197 with SMTP id h5mr16966843pat.29.1432308725096; Fri, 22 May 2015 08:32:05 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id as1sm2474485pbc.39.2015.05.22.08.31.58 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 May 2015 08:32:04 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 09/12] ARM: imx: get rid of variable timer_base Date: Fri, 22 May 2015 23:29:56 +0800 Message-Id: <1432308599-28643-10-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> References: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150522_083226_397266_D83B2911 X-CRM114-Status: GOOD ( 16.33 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.192.180 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.1 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.180 listed in wl.mailspike.net] Cc: Shawn Guo , Daniel Lezcano , Arnd Bergmann , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org We now have pointer to imx_timer structure available where timer base address is needed, so we can just kill global timer_base by using imxtm->base instead. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 55 +++++++++++++++++++++++------------------------- 1 file changed, 26 insertions(+), 29 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index da1ad20d2c1d..a4f12c75050f 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -104,45 +104,43 @@ struct imx_gpt_data { struct clock_event_device *ced); }; -static void __iomem *timer_base; - static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced) { return container_of(ced, struct imx_timer, ced); } -static inline void gpt_irq_disable(void) +static inline void gpt_irq_disable(struct imx_timer *imxtm) { unsigned int tmp; if (timer_is_v2()) - writel_relaxed(0, timer_base + V2_IR); + writel_relaxed(0, imxtm->base + V2_IR); else { - tmp = readl_relaxed(timer_base + MXC_TCTL); - writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); + tmp = readl_relaxed(imxtm->base + MXC_TCTL); + writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); } } -static inline void gpt_irq_enable(void) +static inline void gpt_irq_enable(struct imx_timer *imxtm) { if (timer_is_v2()) - writel_relaxed(1<<0, timer_base + V2_IR); + writel_relaxed(1<<0, imxtm->base + V2_IR); else { - writel_relaxed(readl_relaxed(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, - timer_base + MXC_TCTL); + writel_relaxed(readl_relaxed(imxtm->base + MXC_TCTL) | MX1_2_TCTL_IRQEN, + imxtm->base + MXC_TCTL); } } -static void gpt_irq_acknowledge(void) +static void gpt_irq_acknowledge(struct imx_timer *imxtm) { if (timer_is_v1()) { if (cpu_is_mx1()) - writel_relaxed(0, timer_base + MX1_2_TSTAT); + writel_relaxed(0, imxtm->base + MX1_2_TSTAT); else writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, - timer_base + MX1_2_TSTAT); + imxtm->base + MX1_2_TSTAT); } else if (timer_is_v2()) - writel_relaxed(V2_TSTAT_OF1, timer_base + V2_TSTAT); + writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); } static void __iomem *sched_clock_reg; @@ -178,29 +176,31 @@ static int __init mxc_clocksource_init(struct imx_timer *imxtm) /* clock event */ static int mx1_2_set_next_event(unsigned long evt, - struct clock_event_device *unused) + struct clock_event_device *ced) { + struct imx_timer *imxtm = to_imx_timer(ced); unsigned long tcmp; - tcmp = readl_relaxed(timer_base + MX1_2_TCN) + evt; + tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt; - writel_relaxed(tcmp, timer_base + MX1_2_TCMP); + writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP); - return (int)(tcmp - readl_relaxed(timer_base + MX1_2_TCN)) < 0 ? + return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ? -ETIME : 0; } static int v2_set_next_event(unsigned long evt, - struct clock_event_device *unused) + struct clock_event_device *ced) { + struct imx_timer *imxtm = to_imx_timer(ced); unsigned long tcmp; - tcmp = readl_relaxed(timer_base + V2_TCN) + evt; + tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt; - writel_relaxed(tcmp, timer_base + V2_TCMP); + writel_relaxed(tcmp, imxtm->base + V2_TCMP); return evt < 0x7fffffff && - (int)(tcmp - readl_relaxed(timer_base + V2_TCN)) < 0 ? + (int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ? -ETIME : 0; } @@ -227,7 +227,7 @@ static void mxc_set_mode(enum clock_event_mode mode, local_irq_save(flags); /* Disable interrupt in GPT module */ - gpt_irq_disable(); + gpt_irq_disable(imxtm); if (mode != imxtm->cem) { u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); @@ -235,7 +235,7 @@ static void mxc_set_mode(enum clock_event_mode mode, writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); /* Clear pending interrupt */ - gpt_irq_acknowledge(); + gpt_irq_acknowledge(imxtm); } #ifdef DEBUG @@ -261,7 +261,7 @@ static void mxc_set_mode(enum clock_event_mode mode, * mode switching */ local_irq_save(flags); - gpt_irq_enable(); + gpt_irq_enable(imxtm); local_irq_restore(flags); break; case CLOCK_EVT_MODE_SHUTDOWN: @@ -283,7 +283,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); - gpt_irq_acknowledge(); + gpt_irq_acknowledge(imxtm); ced->event_handler(ced); @@ -387,9 +387,6 @@ static const struct imx_gpt_data imx6dl_gpt_data = { static void __init _mxc_timer_init(struct imx_timer *imxtm) { - /* Temporary */ - timer_base = imxtm->base; - switch (imxtm->type) { case GPT_TYPE_IMX1: imxtm->gpt = &imx1_gpt_data;