From patchwork Tue Sep 16 18:48:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 390160 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E791614001A for ; Wed, 17 Sep 2014 04:54:14 +1000 (EST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XTxr2-0003oL-Tx; Tue, 16 Sep 2014 18:51:56 +0000 Received: from albert.telenet-ops.be ([195.130.137.90]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XTxow-0000jv-K7 for linux-arm-kernel@lists.infradead.org; Tue, 16 Sep 2014 18:49:51 +0000 Received: from ayla.of.borg ([84.193.84.167]) by albert.telenet-ops.be with bizsmtp id rup81o0093cczKo06up8M1; Tue, 16 Sep 2014 20:49:23 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.76) (envelope-from ) id 1XTxoJ-0001jq-Mb; Tue, 16 Sep 2014 20:49:07 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1XTxoQ-0001gA-3u; Tue, 16 Sep 2014 20:49:14 +0200 From: Geert Uytterhoeven To: "Rafael J. Wysocki" , Len Brown , Pavel Machek , Simon Horman , Magnus Damm , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Subject: [PATCH/RFC v2 11/12] ARM: shmobile: r8a7740 dtsi: Add PM QoS device latencies Date: Tue, 16 Sep 2014 20:48:58 +0200 Message-Id: <1410893339-6361-12-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1410893339-6361-1-git-send-email-geert+renesas@glider.be> References: <1410893339-6361-1-git-send-email-geert+renesas@glider.be> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140916_114947_007282_63E344F1 X-CRM114-Status: UNSURE ( 7.80 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -0.4 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.4 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [195.130.137.90 listed in list.dnswl.org] -0.4 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [195.130.137.90 listed in wl.mailspike.net] 0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different Cc: devicetree@vger.kernel.org, Ulf Hansson , Kevin Hilman , Geert Uytterhoeven , linux-pm@vger.kernel.org, linux-sh@vger.kernel.org, Tomasz Figa , linux-kernel@vger.kernel.org, Grygorii Strashko , Philipp Zabel , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org For now use 250 µs, just like the legacy platform code does. Signed-off-by: Geert Uytterhoeven --- v2: - New --- arch/arm/boot/dts/r8a7740.dtsi | 136 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index ed0adeb61a1ad8ec..713170442b7bd4b2 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -26,6 +26,10 @@ reg = <0x0>; clock-frequency = <800000000>; power-domains = <&pd_a3sm>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; }; }; @@ -49,6 +53,10 @@ clocks = <&mstp3_clks R8A7740_CLK_CMT1>; clock-names = "fck"; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; renesas,channels-mask = <0x3f>; @@ -75,6 +83,10 @@ 0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>; power-domains = <&pd_a4s>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; }; /* irqpin1: IRQ8 - IRQ15 */ @@ -97,6 +109,10 @@ 0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>; power-domains = <&pd_a4s>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; }; /* irqpin2: IRQ16 - IRQ23 */ @@ -119,6 +135,10 @@ 0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>; power-domains = <&pd_a4s>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; }; /* irqpin3: IRQ24 - IRQ31 */ @@ -141,6 +161,10 @@ 0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>; power-domains = <&pd_a4s>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; }; ether: ethernet@e9a00000 { @@ -150,6 +174,10 @@ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7740_CLK_GETHER>; power-domains = <&pd_a4s>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; phy-mode = "mii"; #address-cells = <1>; #size-cells = <0>; @@ -167,6 +195,10 @@ 0 204 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7740_CLK_IIC0>; power-domains = <&pd_a4r>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -181,6 +213,10 @@ 0 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7740_CLK_IIC1>; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -191,6 +227,10 @@ clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -201,6 +241,10 @@ clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -211,6 +255,10 @@ clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -221,6 +269,10 @@ clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -231,6 +283,10 @@ clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -241,6 +297,10 @@ clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -251,6 +311,10 @@ clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -261,6 +325,10 @@ clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -271,6 +339,10 @@ clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -290,6 +362,10 @@ <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; }; tpu: pwm@e6600000 { @@ -297,6 +373,10 @@ reg = <0xe6600000 0x100>; clocks = <&mstp3_clks R8A7740_CLK_TPU0>; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; #pwm-cells = <3>; }; @@ -308,6 +388,10 @@ 0 57 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7740_CLK_MMC>; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -319,6 +403,10 @@ 0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -332,6 +420,10 @@ 0 123 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -345,6 +437,10 @@ 0 127 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; power-domains = <&pd_a3sp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -357,6 +453,10 @@ interrupts = <0 9 0x4>; clocks = <&mstp3_clks R8A7740_CLK_FSI>; power-domains = <&pd_a4mp>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; status = "disabled"; }; @@ -409,6 +509,10 @@ reg = <0xe6150000 0x10000>; clocks = <&extal1_clk>, <&extalr_clk>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; #clock-cells = <1>; clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", @@ -424,6 +528,10 @@ reg = <0xe6150080 4>; clocks = <&pllc1_div2_clk>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; #clock-cells = <0>; clock-output-names = "sub"; }; @@ -433,6 +541,10 @@ compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -442,6 +554,10 @@ compatible = "fixed-factor-clock"; clocks = <&extal1_clk>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -454,6 +570,10 @@ reg = <0xe6150080 4>; clocks = <&sub_clk>, <&sub_clk>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; #clock-cells = <1>; renesas,clock-indices = < R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 @@ -470,6 +590,10 @@ <&sub_clk>, <&sub_clk>, <&cpg_clocks R8A7740_CLK_B>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; #clock-cells = <1>; renesas,clock-indices = < R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 @@ -492,6 +616,10 @@ <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; #clock-cells = <1>; renesas,clock-indices = < R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA @@ -522,6 +650,10 @@ <&cpg_clocks R8A7740_CLK_HP>, <&cpg_clocks R8A7740_CLK_HP>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; #clock-cells = <1>; renesas,clock-indices = < R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 @@ -540,6 +672,10 @@ <&cpg_clocks R8A7740_CLK_HP>, <&cpg_clocks R8A7740_CLK_HP>; power-domains = <&pd_c5>; + stop-latency = <250000>; + start-latency = <250000>; + save-state-latency = <250000>; + restore-state-latency = <250000>; #clock-cells = <1>; renesas,clock-indices = < R8A7740_CLK_USBH R8A7740_CLK_SDHI2