From patchwork Mon Jul 28 03:49:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Emilio_L=C3=B3pez?= X-Patchwork-Id: 374075 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id BF1BD140191 for ; Mon, 28 Jul 2014 13:53:37 +1000 (EST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBbxc-0004lK-QZ; Mon, 28 Jul 2014 03:50:52 +0000 Received: from yotta.elopez.com.ar ([2a00:1768:1004:d00d:c0de:4:f00d:cafe]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1XBbxR-0004if-Ry for linux-arm-kernel@lists.infradead.org; Mon, 28 Jul 2014 03:50:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=elopez.com.ar; s=mail; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=VE2fP8VkOVcdmFeelsyXysV+JJEDhrFwS0lJ8NpJU8Y=; b=NqAqrItX7sPeEYF0FgXr8lcU3DXopSn7c/UObfyqEeYgOJexx0ED8kvz0Si/0vWPjQnGIUO0HNhlApH/ABp9/uLDIO64Oc76PsskxbSV5IUNXv2Vu5Un0zau43oMwKOTjsLb0iGg9sDt8kSGTyBoCJwgYRbOeRGYl5MPqFLdSh6rwBrh/NMIJUCX0ERN9L8SaZuybIMyuxOTl1M24aHahL7vBz4qJx8ijKxvfo9nrvbI7R1RsPNP9B2uOr6q/qk1sz8wiCsl66Q3jJQX+eZDGrDlaWEdZqUePAN+onrDqqSvxm7MgDg4z6SUeBlY7t7twcAkv5ZizRQuXe5Kp5D+NQ==; Received: from [181.164.71.8] (helo=desktop.lan) by yotta.elopez.com.ar with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_CBC_SHA256:128) (Exim 4.82_1-5b7a7c0-XX) id 1XBbx0-0005pY-6U; Mon, 28 Jul 2014 00:50:14 -0300 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= To: Maxime Ripard , Mike Turquette Subject: [RFC 1/8] clk: sunxi: PLL2 support for sun4i, sun5i and sun7i Date: Mon, 28 Jul 2014 00:49:39 -0300 Message-Id: <1406519386-4902-2-git-send-email-emilio@elopez.com.ar> X-Mailer: git-send-email 2.0.3 In-Reply-To: <1406519386-4902-1-git-send-email-emilio@elopez.com.ar> References: <1406519386-4902-1-git-send-email-emilio@elopez.com.ar> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140727_205042_294512_3B1467EE X-CRM114-Status: GOOD ( 13.32 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.6 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: =?UTF-8?q?Emilio=20L=C3=B3pez?= , codekipper@gmail.com, Chen-Yu Tsai , jonsmirl@gmail.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org This patch adds support for PLL2 and derivates on A10 revision B and higher, as well as on sun5i and sun7i SoCs. As this PLL is only used for audio and requires good accuracy, we only support two known good rates. Signed-off-by: Emilio López --- drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk-a10-pll2.c | 249 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 250 insertions(+) create mode 100644 drivers/clk/sunxi/clk-a10-pll2.c diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 6850cba..dcd5709 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -4,6 +4,7 @@ obj-y += clk-sunxi.o clk-factors.o obj-y += clk-a10-hosc.o +obj-y += clk-a10-pll2.o obj-y += clk-a20-gmac.o obj-$(CONFIG_MFD_SUN6I_PRCM) += \ diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c new file mode 100644 index 0000000..bdbf1e9 --- /dev/null +++ b/drivers/clk/sunxi/clk-a10-pll2.c @@ -0,0 +1,249 @@ +/* + * Copyright 2013 Emilio López + * + * Emilio López + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define SUN4I_PLL2_ENABLE 31 +#define SUN4I_PLL2_POST_DIV 26 +#define SUN4I_PLL2_POST_DIV_MASK 0xF +#define SUN4I_PLL2_N 8 +#define SUN4I_PLL2_N_MASK 0x7F +#define SUN4I_PLL2_PRE_DIV 0 +#define SUN4I_PLL2_PRE_DIV_MASK 0x1F + +#define SUN4I_PLL2_OUTPUTS 4 + +struct sun4i_pll2_clk { + struct clk_hw hw; + void __iomem *reg; +}; + +static inline struct sun4i_pll2_clk *to_sun4i_pll2_clk(struct clk_hw *hw) +{ + return container_of(hw, struct sun4i_pll2_clk, hw); +} + +static unsigned long sun4i_pll2_1x_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw); + int n, prediv, postdiv; + + u32 val = readl(clk->reg); + n = (val >> SUN4I_PLL2_N) & SUN4I_PLL2_N_MASK; + prediv = (val >> SUN4I_PLL2_PRE_DIV) & SUN4I_PLL2_PRE_DIV_MASK; + postdiv = (val >> SUN4I_PLL2_POST_DIV) & SUN4I_PLL2_POST_DIV_MASK; + + /* 0 is a special case and means 1 */ + if (n == 0) + n = 1; + if (prediv == 0) + prediv = 1; + if (postdiv == 0) + postdiv = 1; + + return ((parent_rate * n) / prediv) / postdiv; +} + +static unsigned long sun4i_pll2_8x_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw); + int n, prediv; + + u32 val = readl(clk->reg); + n = (val >> SUN4I_PLL2_N) & SUN4I_PLL2_N_MASK; + prediv = (val >> SUN4I_PLL2_PRE_DIV) & SUN4I_PLL2_PRE_DIV_MASK; + + /* 0 is a special case and means 1 */ + if (n == 0) + n = 1; + if (prediv == 0) + prediv = 1; + + return ((parent_rate * 2 * n) / prediv); +} + +static unsigned long sun4i_pll2_4x_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return sun4i_pll2_8x_recalc_rate(hw, parent_rate / 2); +} + +static unsigned long sun4i_pll2_2x_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return sun4i_pll2_8x_recalc_rate(hw, parent_rate / 4); +} + +static long sun4i_pll2_1x_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + /* + * There is only two interesting rates for the audio PLL, the + * rest isn't really usable due to accuracy concerns. Therefore, + * we specifically round to those rates here + */ + if (rate < 22579200) + return -EINVAL; + + if (rate >= 22579200 && rate < 24576000) + return 22579200; + + return 24576000; +} + +static long sun4i_pll2_8x_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + /* + * We should account for the postdiv that we're undoing on PLL2x8, + * which is always 4 in the usable configurations. The division + * by two is done because PLL2x8 also doubles the rate + */ + *parent_rate = (rate * 4) / 2; + + return rate; +} + +static long sun4i_pll2_4x_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + /* PLL2x4 * 2 = PLL2x8 */ + return sun4i_pll2_8x_round_rate(hw, rate * 2, parent_rate); +} + +static long sun4i_pll2_2x_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + /* PLL2x2 * 4 = PLL2x8 */ + return sun4i_pll2_8x_round_rate(hw, rate * 4, parent_rate); +} + +static int sun4i_pll2_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct sun4i_pll2_clk *clk = to_sun4i_pll2_clk(hw); + u32 val = readl(clk->reg); + + val &= ~(SUN4I_PLL2_N_MASK << SUN4I_PLL2_N); + val &= ~(SUN4I_PLL2_PRE_DIV_MASK << SUN4I_PLL2_PRE_DIV); + val &= ~(SUN4I_PLL2_POST_DIV_MASK << SUN4I_PLL2_POST_DIV); + + val |= (21 << SUN4I_PLL2_PRE_DIV) | (4 << SUN4I_PLL2_POST_DIV); + + if (rate == 22579200) + val |= (79 << SUN4I_PLL2_N); + else if (rate == 24576000) + val |= (86 << SUN4I_PLL2_N); + else + return -EINVAL; + + writel(val, clk->reg); + + return 0; +} + +static struct clk_ops sun4i_pll2_ops_1x = { + .recalc_rate = sun4i_pll2_1x_recalc_rate, + .round_rate = sun4i_pll2_1x_round_rate, + .set_rate = sun4i_pll2_set_rate, +}; + +static struct clk_ops sun4i_pll2_ops_2x = { + .recalc_rate = sun4i_pll2_2x_recalc_rate, + .round_rate = sun4i_pll2_2x_round_rate, +}; + +static struct clk_ops sun4i_pll2_ops_4x = { + .recalc_rate = sun4i_pll2_4x_recalc_rate, + .round_rate = sun4i_pll2_4x_round_rate, +}; + +static struct clk_ops sun4i_pll2_ops_8x = { + .recalc_rate = sun4i_pll2_8x_recalc_rate, + .round_rate = sun4i_pll2_8x_round_rate, +}; + +static void __init sun4i_pll2_setup(struct device_node *np) +{ + const char *clk_name = np->name, *parent; + struct clk_onecell_data *clk_data; + struct sun4i_pll2_clk *pll2; + struct clk_gate *gate; + struct clk **clks; + void __iomem *reg; + + pll2 = kzalloc(sizeof(*pll2), GFP_KERNEL); + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); + clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL); + if (!pll2 || !gate || !clk_data || !clks) + goto free_mem; + + reg = of_iomap(np, 0); + parent = of_clk_get_parent_name(np, 0); + of_property_read_string_index(np, "clock-output-names", 0, &clk_name); + + pll2->reg = reg; + gate->reg = reg; + gate->bit_idx = SUN4I_PLL2_ENABLE; + + /* PLL2, also known as PLL2x1 */ + of_property_read_string_index(np, "clock-output-names", 0, &clk_name); + clks[0] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL, + &pll2->hw, &sun4i_pll2_ops_1x, + &gate->hw, &clk_gate_ops, 0); + WARN_ON(IS_ERR(clks[0])); + parent = clk_name; + + /* PLL2x2, 1/4 the rate of PLL2x8 */ + of_property_read_string_index(np, "clock-output-names", 1, &clk_name); + clks[1] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL, + &pll2->hw, &sun4i_pll2_ops_2x, + NULL, NULL, CLK_SET_RATE_PARENT); + WARN_ON(IS_ERR(clks[1])); + + /* PLL2x4, 1/2 the rate of PLL2x8 */ + of_property_read_string_index(np, "clock-output-names", 2, &clk_name); + clks[2] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL, + &pll2->hw, &sun4i_pll2_ops_4x, + NULL, NULL, CLK_SET_RATE_PARENT); + WARN_ON(IS_ERR(clks[2])); + + /* PLL2x8, double of PLL2 without the post divisor */ + of_property_read_string_index(np, "clock-output-names", 3, &clk_name); + clks[3] = clk_register_composite(NULL, clk_name, &parent, 1, NULL, NULL, + &pll2->hw, &sun4i_pll2_ops_8x, + NULL, NULL, CLK_SET_RATE_PARENT); + WARN_ON(IS_ERR(clks[3])); + + clk_data->clks = clks; + clk_data->clk_num = SUN4I_PLL2_OUTPUTS; + of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); + + return; + +free_mem: + kfree(pll2); + kfree(gate); + kfree(clk_data); + kfree(clks); +} +CLK_OF_DECLARE(sun4i_pll2, "allwinner,sun4i-a10-b-pll2-clk", sun4i_pll2_setup);