From patchwork Fri Nov 1 09:02:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 287745 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 360DD2C00E2 for ; Fri, 1 Nov 2013 20:11:19 +1100 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VcAkK-0004ci-Ue; Fri, 01 Nov 2013 09:10:25 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VcAkF-0001Q2-5I; Fri, 01 Nov 2013 09:10:19 +0000 Received: from mail-db8lp0186.outbound.messaging.microsoft.com ([213.199.154.186] helo=db8outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VcAcv-0004Jz-B1 for linux-arm-kernel@lists.infradead.org; Fri, 01 Nov 2013 09:02:46 +0000 Received: from mail128-db8-R.bigfish.com (10.174.8.240) by DB8EHSOBE012.bigfish.com (10.174.4.75) with Microsoft SMTP Server id 14.1.225.22; Fri, 1 Nov 2013 09:02:16 +0000 Received: from mail128-db8 (localhost [127.0.0.1]) by mail128-db8-R.bigfish.com (Postfix) with ESMTP id 4728C16013A; Fri, 1 Nov 2013 09:02:16 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275dh1de097hz2dh87h2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h1151h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail128-db8 (localhost.localdomain [127.0.0.1]) by mail128-db8 (MessageSwitch) id 1383296534280147_26189; Fri, 1 Nov 2013 09:02:14 +0000 (UTC) Received: from DB8EHSMHS029.bigfish.com (unknown [10.174.8.254]) by mail128-db8.bigfish.com (Postfix) with ESMTP id 402E74E0075; Fri, 1 Nov 2013 09:02:14 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS029.bigfish.com (10.174.4.39) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 1 Nov 2013 09:02:14 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.3.158.2; Fri, 1 Nov 2013 09:02:12 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.19]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id rA1923MF019762; Fri, 1 Nov 2013 02:02:10 -0700 From: Shawn Guo To: Subject: [PATCH 3/3] ARM: imx: set up pllv3 POWER and BYPASS sequentially Date: Fri, 1 Nov 2013 17:02:25 +0800 Message-ID: <1383296545-18652-4-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1383296545-18652-1-git-send-email-shawn.guo@linaro.org> References: <1383296545-18652-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20131101_050245_503600_AAC98CD5 X-CRM114-Status: GOOD ( 12.54 ) X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [213.199.154.186 listed in list.dnswl.org] 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Shawn Guo , Russell King - ARM Linux X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Currently, POWER and BYPASS bits are set up in a single write to pllv3 register. This causes problem occasionally from the IPU/HDMI testing. Let's follow FSL BSP code to set up POWER bit, relock, and then BYPASS sequentially. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/clk-pllv3.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index df17362..6136405 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -71,16 +71,24 @@ static int clk_pllv3_prepare(struct clk_hw *hw) { struct clk_pllv3 *pll = to_clk_pllv3(hw); u32 val; + int ret; val = readl_relaxed(pll->base); - val &= ~BM_PLL_BYPASS; if (pll->powerup_set) val |= BM_PLL_POWER; else val &= ~BM_PLL_POWER; writel_relaxed(val, pll->base); - return clk_pllv3_wait_lock(pll); + ret = clk_pllv3_wait_lock(pll); + if (ret) + return ret; + + val = readl_relaxed(pll->base); + val &= ~BM_PLL_BYPASS; + writel_relaxed(val, pll->base); + + return 0; } static void clk_pllv3_unprepare(struct clk_hw *hw)