From patchwork Fri May 31 22:42:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 248035 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2EB872C007E for ; Sat, 1 Jun 2013 08:44:44 +1000 (EST) Received: from merlin.infradead.org ([205.233.59.134]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UiY2b-0004P7-5s; Fri, 31 May 2013 22:43:22 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1UiY25-0004nh-P9; Fri, 31 May 2013 22:42:49 +0000 Received: from mail-yh0-x236.google.com ([2607:f8b0:4002:c01::236]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1UiY1v-0004mJ-AQ for linux-arm-kernel@lists.infradead.org; Fri, 31 May 2013 22:42:40 +0000 Received: by mail-yh0-f54.google.com with SMTP id f11so571604yha.27 for ; Fri, 31 May 2013 15:42:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=DCDc5eJiQAVaENKF6UEWYqCRID5L9w1j31l9Dp11HCU=; b=SViz8/7QDbIPYRa/a/8X27ayeHwfYH5JFfz/lIeVTG/SRgKVWeEPKwEbkY6CRDWSsc yuXCpQFTvZ0E5+hToDbH45zdXRjW6SNiabRw130DCubUy9twr4QFQJy/QMp47E0kcLQj pol0OH1XAlSMQDBPWY9Q6u+7VTQ8smJhrEpbqKGu/lY5tVzwjjJ+/o7idrM4RsI4Ry3R 4Rfz6ZXlJOL7OrBFio+yd1GGGDSbn/ifgkub2Gw8MPKadl49ptob/Fu0XzGffTO3AEIw xa91DZOyaqk/NXhKaJPMaj/qVPQrjwI/3CUYt06cQP6hrd2D1O625Zo2Z3Vm5iw92Yrs ghYg== X-Received: by 10.236.160.3 with SMTP id t3mr8249085yhk.19.1370040136781; Fri, 31 May 2013 15:42:16 -0700 (PDT) Received: from localhost.localdomain ([189.101.179.164]) by mx.google.com with ESMTPSA id m74sm70881008yhm.0.2013.05.31.15.42.15 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 May 2013 15:42:16 -0700 (PDT) From: Fabio Estevam To: shawn.guo@linaro.org Subject: [PATCH v2 1/2] ARM: mxs: Print silicon version on boot Date: Fri, 31 May 2013 19:42:06 -0300 Message-Id: <1370040127-15072-1-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.8.1.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130531_184239_476557_BF342F94 X-CRM114-Status: GOOD ( 14.09 ) X-Spam-Score: -2.0 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (festevam[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Fabio Estevam , linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org From: Fabio Estevam Introduce functions that identify the SoC type (i.MX23 or iMX28) and also report the silicon revision. Signed-off-by: Fabio Estevam --- Changes since v1: - Use MXS as prefix in the revision definitions - Retrieve the base address from dt - Remove unneeded blank line - Treat 0x0 as TO1.1 - Use u32 arch/arm/mach-mxs/mach-mxs.c | 86 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 66fe810..462fa14 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c @@ -38,12 +38,27 @@ #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3 +#define HW_DIGCTL_CHIPID 0x310 +#define HW_DIGCTL_CHIPID_MASK (0xffff << 16) +#define HW_DIGCTL_REV_MASK 0xff +#define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) +#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) + +#define MXS_CHIP_REVISION_1_0 0x10 +#define MXS_CHIP_REVISION_1_1 0x11 +#define MXS_CHIP_REVISION_1_2 0x12 +#define MXS_CHIP_REVISION_1_3 0x13 +#define MXS_CHIP_REVISION_1_4 0x14 +#define MXS_CHIP_REV_UNKNOWN 0xff + #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr)) #define MXS_SET_ADDR 0x4 #define MXS_CLR_ADDR 0x8 #define MXS_TOG_ADDR 0xc +static void __iomem *digctl_base; + static inline void __mxs_setl(u32 mask, void __iomem *reg) { __raw_writel(mask, reg + MXS_SET_ADDR); @@ -361,8 +376,79 @@ static void __init cfa10037_init(void) update_fec_mac_prop(OUI_CRYSTALFONTZ); } +static const char *mxs_get_cpu_type(void) +{ + u32 reg; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl"); + digctl_base = of_iomap(np, 0); + WARN_ON(!digctl_base); + + reg = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_CHIPID_MASK; + switch (reg) { + case HW_DIGCTL_CHIPID_MX23: + return "23"; + case HW_DIGCTL_CHIPID_MX28: + return "28"; + default: + return "unknown"; + } +} + +static int mxs_get_cpu_rev(void) +{ + u32 reg, rev; + + reg = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_CHIPID_MASK; + rev = readl(digctl_base + HW_DIGCTL_CHIPID) & HW_DIGCTL_REV_MASK; + + switch (reg) { + case HW_DIGCTL_CHIPID_MX23: + switch (rev) { + case 0x0: + return MXS_CHIP_REVISION_1_0; + case 0x1: + return MXS_CHIP_REVISION_1_1; + case 0x2: + return MXS_CHIP_REVISION_1_2; + case 0x3: + return MXS_CHIP_REVISION_1_3; + case 0x4: + return MXS_CHIP_REVISION_1_4; + default: + return MXS_CHIP_REV_UNKNOWN; + } + case HW_DIGCTL_CHIPID_MX28: + switch (rev) { + case 0x0: + return MXS_CHIP_REVISION_1_1; + case 0x1: + return MXS_CHIP_REVISION_1_2; + default: + return MXS_CHIP_REV_UNKNOWN; + } + default: + return MXS_CHIP_REV_UNKNOWN; + } +} + +static void mxs_print_silicon_rev(const char *cpu, int srev) +{ + if (srev == MXS_CHIP_REV_UNKNOWN) + pr_info("CPU identified as i.MX%s, unknown revision\n", cpu); + else + pr_info("CPU identified as i.MX%s, silicon rev %d.%d\n", + cpu, (srev >> 4) & 0xf, srev & 0xf); +} + static void __init mxs_machine_init(void) { + const char *cpu_char = mxs_get_cpu_type(); + int cpu_rev = mxs_get_cpu_rev(); + + mxs_print_silicon_rev(cpu_char, cpu_rev); + if (of_machine_is_compatible("fsl,imx28-evk")) imx28_evk_init(); else if (of_machine_is_compatible("bluegiga,apx4devkit"))