From patchwork Thu Dec 15 15:53:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 131684 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 763491007D4 for ; Fri, 16 Dec 2011 02:58:07 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1RbDeZ-00026I-S1; Thu, 15 Dec 2011 15:55:27 +0000 Received: from mail-fx0-f49.google.com ([209.85.161.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RbDdj-0001se-0z for linux-arm-kernel@lists.infradead.org; Thu, 15 Dec 2011 15:54:38 +0000 Received: by mail-fx0-f49.google.com with SMTP id n18so1019848fag.36 for ; Thu, 15 Dec 2011 07:54:34 -0800 (PST) Received: by 10.180.19.138 with SMTP id f10mr5976391wie.53.1323964474630; Thu, 15 Dec 2011 07:54:34 -0800 (PST) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id 28sm9930801wby.3.2011.12.15.07.54.32 (version=SSLv3 cipher=OTHER); Thu, 15 Dec 2011 07:54:33 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 5/5] imx6q: Remove unconditional dependency on l2x0 L2 cache support Date: Thu, 15 Dec 2011 15:53:54 +0000 Message-Id: <1323964434-6764-6-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1323964434-6764-1-git-send-email-dave.martin@linaro.org> References: <1323964434-6764-1-git-send-email-dave.martin@linaro.org> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Will Deacon , Kukjin Kim , Pawel Moll , patches@linaro.org, linux-sh@vger.kernel.org, Catalin Marinas , Linus Walleij , Anton Vorontsov , Magnus Damm , Haojian Zhuang , Colin Cross , Shawn Guo , Tony Lindgren , Paul Mundt , linux-samsung-soc@vger.kernel.org, Rob Herring , Sascha Hauer , Barry Song , linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, John Linn X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The i.MX6 Quad SoC will work without the l2x0 L2 cache controller support built into the kernel, so this patch removes the dependency on CACHE_L2X0. This makes the l2x0 support optional, so that it can be turned off when desired for debugging purposes etc. Since SOC_IMX6Q already depends on ARCH_IMX_V6_V7 and ARCH_IMX_V6_V7 selects MIGHT_HAVE_CACHE_L2X0, there is no need to select that option explicitly from SOC_IMX6Q. Thanks to Shawn Guo for this suggestion. [1] [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074602.html Signed-off-by: Dave Martin --- Changes: v5: Don't select MIGHT_HAVE_CACHE_L2X0 directly from SOC_IMX6Q, but instead select implicitly via ARCH_IMX_V6_V7 (which we expect to be selected by other relevant SoCs). Thanks to Shawn for this suggestion. arch/arm/mach-imx/Kconfig | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 29a3d61..1530678 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -609,7 +609,6 @@ comment "i.MX6 family:" config SOC_IMX6Q bool "i.MX6 Quad support" select ARM_GIC - select CACHE_L2X0 select CPU_V7 select HAVE_ARM_SCU select HAVE_IMX_GPC