From patchwork Thu Jun 11 09:35:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander A Sverdlin X-Patchwork-Id: 483024 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C74E414029E for ; Thu, 11 Jun 2015 19:35:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752420AbbFKJfk (ORCPT ); Thu, 11 Jun 2015 05:35:40 -0400 Received: from demumfd001.nsn-inter.net ([93.183.12.32]:46495 "EHLO demumfd001.nsn-inter.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751190AbbFKJfj (ORCPT ); Thu, 11 Jun 2015 05:35:39 -0400 Received: from demuprx017.emea.nsn-intra.net ([10.150.129.56]) by demumfd001.nsn-inter.net (8.15.1/8.15.1) with ESMTPS id t5B9ZY76008488 (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 11 Jun 2015 09:35:34 GMT Received: from [10.151.38.21] ([10.151.38.21]) by demuprx017.emea.nsn-intra.net (8.12.11.20060308/8.12.11) with ESMTP id t5B9ZQM9003313; Thu, 11 Jun 2015 11:35:26 +0200 Message-ID: <5579565E.1020908@nokia.com> Date: Thu, 11 Jun 2015 11:35:26 +0200 From: Alexander Sverdlin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: Sekhar Nori , Kevin Hilman , Wolfram Sang , linux-i2c@vger.kernel.org CC: "Lawnick, Michael (Nokia - DE/Ulm)" Subject: [PATCH] i2c: davinci: Optimize SCL generation X-purgate-type: clean X-purgate-Ad: Categorized by eleven eXpurgate (R) http://www.eleven.de X-purgate: clean X-purgate: This mail is considered clean (visit http://www.eleven.de for further information) X-purgate-size: 2433 X-purgate-ID: 151667::1434015334-00006B28-32D90560/0/0 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org There are several cases where current clock configuration algorithm produces not optimal results: - truncation in "clk" calculation leads to the fact that actual BUS frequency will be always higher than spec except two exact module frequences 8MHz and 12MHz in the whole 7-12MHz range of permitted frequences - driver configures SCL HIGH to LOW ratio always 1 to 1 and this doesn't work well in 400kHz case, namely minimum time of LOW state (according to I2C Spec 2.1) 1.3us will not be fulfilled. HIGH to LOW ratio 1 to 2 would be more approriate here. Signed-off-by: Michael Lawnick Signed-off-by: Alexander Sverdlin --- Tested on custom Keystone II SoC-based board with complicated I2C network working on the edge of its HW specs (signal quality). In this case 1 to 2 HIGH to LOW relation really improves the reliability with 400kHz bus rate. drivers/i2c/busses/i2c-davinci.c | 27 ++++++++++++++++++++++++--- 1 files changed, 24 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-i2c" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c index e35c9df..4a110af 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c @@ -211,9 +211,30 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) psc++; /* better to run under spec than over */ d = (psc >= 2) ? 5 : 7 - psc; - clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1); - clkh = clk >> 1; - clkl = clk - clkh; + clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)); + /* Avoid driving the bus too fast because of rounding errors above */ + if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000) + clk++; + /* + * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at + * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH + * to LOW ratio as 1 to 2 is more safe. + */ + if (pdata->bus_freq > 100) + clkl = (clk << 1) / 3; + else + clkl = (clk >> 1); + /* + * It's not always possible to have 1 to 2 ratio when d=7, so fall back + * to minimal possible clkh in this case. + */ + if (clk >= clkl + d) { + clkh = clk - clkl - d; + clkl -= d; + } else { + clkh = 0; + clkl = clk - (d << 1); + } davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc); davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);