| Message ID | 20220207162637.1658677-4-conor.dooley@microchip.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | Update the Icicle Kit device tree | expand |
On Mon, Feb 07, 2022 at 04:26:29PM +0000, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Add device tree bindings for the i2c controller on > the Microchip PolarFire SoC. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Shall this go via DT (Rob) or I2C (me) or some riscv tree?
On 08/02/2022 12:18, Wolfram Sang wrote: > On Mon, Feb 07, 2022 at 04:26:29PM +0000, conor.dooley@microchip.com wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> Add device tree bindings for the i2c controller on >> the Microchip PolarFire SoC. >> >> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> >> Reviewed-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > Shall this go via DT (Rob) or I2C (me) or some riscv tree? If you could take it, that'd be great. Rob had said via subsystems was his preference for the bindings in this series. Thanks, Conor.
On Mon, Feb 07, 2022 at 04:26:29PM +0000, conor.dooley@microchip.com wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > Add device tree bindings for the i2c controller on > the Microchip PolarFire SoC. > > Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Applied to for-next, thanks!
diff --git a/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml new file mode 100644 index 000000000000..c8e605fbb8a6 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/microchip,corei2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS I2C Controller Device Tree Bindings + +maintainers: + - Daire McNamara <daire.mcnamara@microchip.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs + - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core + - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: | + Desired I2C bus clock frequency in Hz. As only Standard and Fast + modes are supported, possible values are 100000 and 400000. + enum: [100000, 400000] + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c@2010a000 { + compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; + reg = <0x2010a000 0x1000>; + clocks = <&clkcfg 15>; + interrupt-parent = <&plic>; + interrupts = <58>; + clock-frequency = <100000>; + }; +...