From patchwork Fri Aug 26 13:09:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 663103 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sLM4p66yLz9stY for ; Fri, 26 Aug 2016 23:16:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753411AbcHZNPz (ORCPT ); Fri, 26 Aug 2016 09:15:55 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16822 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753267AbcHZNPx (ORCPT ); Fri, 26 Aug 2016 09:15:53 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 26 Aug 2016 06:09:15 -0700 Received: from HQMAIL101.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 26 Aug 2016 06:05:31 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 26 Aug 2016 06:05:31 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 26 Aug 2016 13:09:48 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Fri, 26 Aug 2016 13:09:48 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.26.11.251]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Fri, 26 Aug 2016 06:09:45 -0700 From: Jon Hunter To: Laxman Dewangan , Wolfram Sang CC: Stephen Warren , Thierry Reding , Alexandre Courbot , , , , Jon Hunter Subject: [PATCH V2 9/9] i2c: tegra: Add pinctrl support Date: Fri, 26 Aug 2016 14:09:05 +0100 Message-ID: <1472216945-11818-10-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1472216945-11818-1-git-send-email-jonathanh@nvidia.com> References: <1472216945-11818-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org On Tegra124/132 the pins for I2C6 are shared with the Display Port AUX (DPAUX) channel and on Tegra210 the pins for I2C4 and I2C6 are shared with DPAUX1 and DPAUX0, respectively. The multiplexing of the pins is handled by a register in the DPAUX and so the Tegra DPAUX driver has been updated to register a pinctrl device for managing these pins. The pins for these particular I2C devices are bound to the I2C device prior to probing. However, these I2C devices are in a different power partition to the DPAUX devices that own the pins. Hence, it is desirable to place the pins in the 'idle' state and allow the DPAUX power partition to switch off, when these I2C devices is not in use. Therefore, add calls to place the I2C pins in the 'default' and 'idle' states when the I2C device is runtime resumed and suspended, respectively. Please note that the pinctrl functions that set the state of the pins check to see if the devices has pins associated and will return zero if they do not. Therefore, it is safe to call these pinctrl functions even for I2C devices that do not have any pins associated. Signed-off-by: Jon Hunter Acked-by: Laxman Dewangan Reviewed-by: Linus Walleij --- drivers/i2c/busses/i2c-tegra.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 05e34dc29d5a..d86a993b75d6 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -407,6 +408,10 @@ static int tegra_i2c_runtime_resume(struct device *dev) struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); int ret; + ret = pinctrl_pm_select_default_state(i2c_dev->dev); + if (ret) + return ret; + if (!i2c_dev->hw->has_single_clk_source) { ret = clk_enable(i2c_dev->fast_clk); if (ret < 0) { @@ -435,7 +440,7 @@ static int tegra_i2c_runtime_suspend(struct device *dev) if (!i2c_dev->hw->has_single_clk_source) clk_disable(i2c_dev->fast_clk); - return 0; + return pinctrl_pm_select_idle_state(i2c_dev->dev); } static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)