From patchwork Fri Oct 3 15:35:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhangfei Gao X-Patchwork-Id: 396282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4D49E14017D for ; Sat, 4 Oct 2014 01:44:36 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753298AbaJCPof (ORCPT ); Fri, 3 Oct 2014 11:44:35 -0400 Received: from mail-pa0-f43.google.com ([209.85.220.43]:56758 "EHLO mail-pa0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753120AbaJCPoe (ORCPT ); Fri, 3 Oct 2014 11:44:34 -0400 Received: by mail-pa0-f43.google.com with SMTP id lf10so1725593pab.2 for ; Fri, 03 Oct 2014 08:44:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IvBFQECaiuDQYcI/+4AvfJelDUC+xMjTaXzegxKdxnI=; b=SIrXvv+1lWKnHB7GZhDUWH69kolb/VaoZPaTWClY5Na2UbBzblAJ63ndl6qpFD80H0 LOJl2MsoTA09jm7HKJbe2va2Spc+M6nQ4sotr+7Ne31l6uXCA0+OFv46aZ6e3fXLMNLA sS6nMv2I/Fv501C21VVdPfYH3mBs8Og+YesWEviAW7KQo+ydFwv/JEakvG86lGlESop1 znVWKb4648jW6eSWMQUYFCfolt9O97ZnNK0cZWpz7JeudDS0vf63+tj37UvOtIqojl5m XUCBbY1JGIfgcjYxZSPZcV20X4fMUmxN7RMdACLHBjLQb4aSNwSNHIpYhLXAUSUxbjoA xMvg== X-Gm-Message-State: ALoCoQltBs3a6MkVVyT1hnxNvBl4UeDDi1HxGXKeEkyZTwKrOAgNe2NiX9iJw5zDJ8pK/Ed/NHhz X-Received: by 10.69.31.193 with SMTP id ko1mr7896450pbd.110.1412351073867; Fri, 03 Oct 2014 08:44:33 -0700 (PDT) Received: from localhost.localdomain ([60.168.125.194]) by mx.google.com with ESMTPSA id qc3sm6757422pab.48.2014.10.03.08.42.35 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 03 Oct 2014 08:44:32 -0700 (PDT) From: Zhangfei Gao To: Wolfram Sang , Arnd Bergmann , haifeng.yan@linaro.org, jchxue@gmail.com, xuwei5@hisilicon.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-i2c@vger.kernel.org, Zhangfei Gao Subject: [PATCH v4 3/3] ARM: dts: hix5hd2: add i2c node Date: Fri, 3 Oct 2014 23:35:49 +0800 Message-Id: <1412350549-2607-4-git-send-email-zhangfei.gao@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1412350549-2607-1-git-send-email-zhangfei.gao@linaro.org> References: <1412350549-2607-1-git-send-email-zhangfei.gao@linaro.org> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Signed-off-by: Zhangfei Gao --- arch/arm/boot/dts/hisi-x5hd2.dtsi | 60 +++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index d3d99fb..17d0637 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -476,5 +476,65 @@ interrupts = <0 70 4>; clocks = <&clock HIX5HD2_SATA_CLK>; }; + + i2c0: i2c@b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb10000 0x1000>; + interrupts = <0 38 4>; + clocks = <&clock HIX5HD2_I2C0_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb11000 0x1000>; + interrupts = <0 39 4>; + clocks = <&clock HIX5HD2_I2C1_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb12000 0x1000>; + interrupts = <0 40 4>; + clocks = <&clock HIX5HD2_I2C2_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb13000 0x1000>; + interrupts = <0 41 4>; + clocks = <&clock HIX5HD2_I2C3_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@b16000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb16000 0x1000>; + interrupts = <0 43 4>; + clocks = <&clock HIX5HD2_I2C4_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@b17000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb17000 0x1000>; + interrupts = <0 44 4>; + clocks = <&clock HIX5HD2_I2C5_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; };