From patchwork Fri Mar 7 14:12:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chew, Chiau Ee" X-Patchwork-Id: 327816 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E50D02C032A for ; Fri, 7 Mar 2014 17:11:53 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751086AbaCGGKu (ORCPT ); Fri, 7 Mar 2014 01:10:50 -0500 Received: from mga01.intel.com ([192.55.52.88]:51678 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751012AbaCGGKu (ORCPT ); Fri, 7 Mar 2014 01:10:50 -0500 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 06 Mar 2014 22:10:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,605,1389772800"; d="scan'208";a="493970237" Received: from unknown (HELO localhost.png.intel.com) ([172.30.66.71]) by fmsmga002.fm.intel.com with ESMTP; 06 Mar 2014 22:10:48 -0800 From: Chew Chiau Ee To: Wolfram Sang Cc: Mika Westerberg , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C Date: Fri, 7 Mar 2014 22:12:50 +0800 Message-Id: <1394201571-11681-2-git-send-email-chiau.ee.chew@intel.com> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1394201571-11681-1-git-send-email-chiau.ee.chew@intel.com> References: <1394201571-11681-1-git-send-email-chiau.ee.chew@intel.com> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org From: Chew, Chiau Ee All the I2C controllers on Intel BayTrail LPSS subsystem able to support 10-bit addressing mode functionality. Signed-off-by: Chew, Chiau Ee Signed-off-by: Ong, Boon Leong --- drivers/i2c/busses/i2c-designware-pcidrv.c | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c index f1dabee..87f2fc4 100644 --- a/drivers/i2c/busses/i2c-designware-pcidrv.c +++ b/drivers/i2c/busses/i2c-designware-pcidrv.c @@ -64,12 +64,19 @@ struct dw_pci_controller { u32 tx_fifo_depth; u32 rx_fifo_depth; u32 clk_khz; + u32 functionality; }; #define INTEL_MID_STD_CFG (DW_IC_CON_MASTER | \ DW_IC_CON_SLAVE_DISABLE | \ DW_IC_CON_RESTART_EN) +#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ + I2C_FUNC_SMBUS_BYTE | \ + I2C_FUNC_SMBUS_BYTE_DATA | \ + I2C_FUNC_SMBUS_WORD_DATA | \ + I2C_FUNC_SMBUS_I2C_BLOCK) + static struct dw_pci_controller dw_pci_controllers[] = { [moorestown_0] = { .bus_num = 0, @@ -140,6 +147,7 @@ static struct dw_pci_controller dw_pci_controllers[] = { .tx_fifo_depth = 32, .rx_fifo_depth = 32, .clk_khz = 100000, + .functionality = I2C_FUNC_10BIT_ADDR, }, }; static struct i2c_algorithm i2c_dw_algo = { @@ -256,12 +264,9 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev, dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz; dev->base = pcim_iomap_table(pdev)[0]; dev->dev = &pdev->dev; - dev->functionality = - I2C_FUNC_I2C | - I2C_FUNC_SMBUS_BYTE | - I2C_FUNC_SMBUS_BYTE_DATA | - I2C_FUNC_SMBUS_WORD_DATA | - I2C_FUNC_SMBUS_I2C_BLOCK; + dev->functionality = controller->functionality | + DW_DEFAULT_FUNCTIONALITY; + dev->master_cfg = controller->bus_cfg; pci_set_drvdata(pdev, dev);