From patchwork Wed Aug 7 09:05:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingchang Lu X-Patchwork-Id: 265455 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 7D30A2C0219 for ; Wed, 7 Aug 2013 19:59:20 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757282Ab3HGJ7U (ORCPT ); Wed, 7 Aug 2013 05:59:20 -0400 Received: from co9ehsobe005.messaging.microsoft.com ([207.46.163.28]:36714 "EHLO co9outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757265Ab3HGJ7T (ORCPT ); Wed, 7 Aug 2013 05:59:19 -0400 Received: from mail82-co9-R.bigfish.com (10.236.132.242) by CO9EHSOBE022.bigfish.com (10.236.130.85) with Microsoft SMTP Server id 14.1.225.22; Wed, 7 Aug 2013 09:59:18 +0000 Received: from mail82-co9 (localhost [127.0.0.1]) by mail82-co9-R.bigfish.com (Postfix) with ESMTP id AD1DB1A00D3; Wed, 7 Aug 2013 09:59:18 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h8275bh1de097hz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1155h) Received: from mail82-co9 (localhost.localdomain [127.0.0.1]) by mail82-co9 (MessageSwitch) id 1375869556242659_23037; Wed, 7 Aug 2013 09:59:16 +0000 (UTC) Received: from CO9EHSMHS003.bigfish.com (unknown [10.236.132.241]) by mail82-co9.bigfish.com (Postfix) with ESMTP id 2D0FC380047; Wed, 7 Aug 2013 09:59:16 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS003.bigfish.com (10.236.130.13) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 7 Aug 2013 09:59:15 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.136.1; Wed, 7 Aug 2013 09:59:15 +0000 Received: from rock.am.freescale.net (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r779wqx8022506; Wed, 7 Aug 2013 02:59:12 -0700 From: Jingchang Lu To: CC: , , , , , Jingchang Lu Subject: [PATCH 6/8] i2c: imx: add INT flag and IEN bit operatation codes Date: Wed, 7 Aug 2013 17:05:41 +0800 Message-ID: <1375866343-2074-6-git-send-email-b35083@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1375866343-2074-1-git-send-email-b35083@freescale.com> References: <1375866343-2074-1-git-send-email-b35083@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org This add bits operation macro that differ between SoCs. Interrupt flags clear operation in I2SR differ between SoCs: write zero to clear(w0c) INT flag on i.MX, but write one to clear(w1c) INT flag on Vybrid. I2C module enable operation in I2CR also differ between SoCs: set I2CR_IEN bit enable the module on i.MX, but clear I2CR_IEN bit enable the module on Vybrid. Signed-off-by: Jingchang Lu --- drivers/i2c/busses/i2c-imx.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index 8a292a9..dc9f2ec 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c @@ -95,6 +95,22 @@ #define I2CR_IIEN 0x40 #define I2CR_IEN 0x80 +/* register bits different operating codes definition: + * 1) I2SR: Interrupt flags clear operation differ between SoCs: + * - write zero to clear(w0c) INT flag on i.MX, + * - but write one to clear(w1c) INT flag on Vybrid. + * 2) I2CR: I2C module enable operation also differ between SoCs: + * - set I2CR_IEN bit enable the module on i.MX, + * - but clear I2CR_IEN bit enable the module on Vybrid. + */ +#define I2SR_CLR_OPCODE_W0C 0x0 +#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) +#define I2CR_IEN_OPCODE_0 0x0 +#define I2CR_IEN_OPCODE_1 I2CR_IEN + +#define IMX_I2SR_CLR_OPCODE I2SR_CLR_OPCODE_W0C +#define IMX_I2CR_IEN_OPCODE I2CR_IEN_OPCODE_1 + /** Variables ****************************************************************** *******************************************************************************/ @@ -242,8 +258,8 @@ static int i2c_imx_start(struct imx_i2c_struct *i2c_imx) clk_prepare_enable(i2c_imx->clk); imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); /* Enable I2C controller */ - imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); - imx_i2c_write_reg(I2CR_IEN, i2c_imx, IMX_I2C_I2CR); + imx_i2c_write_reg(IMX_I2SR_CLR_OPCODE, i2c_imx, IMX_I2C_I2SR); + imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE, i2c_imx, IMX_I2C_I2CR); /* Wait controller to be stable */ udelay(50); @@ -287,7 +303,7 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx) } /* Disable I2C controller */ - imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); + imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE ^ I2CR_IEN, i2c_imx, IMX_I2C_I2CR); clk_disable_unprepare(i2c_imx->clk); } @@ -339,6 +355,7 @@ static irqreturn_t i2c_imx_isr(int irq, void *dev_id) /* save status register */ i2c_imx->i2csr = temp; temp &= ~I2SR_IIF; + temp |= (IMX_I2SR_CLR_OPCODE & I2SR_IIF); imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); wake_up(&i2c_imx->queue); return IRQ_HANDLED; @@ -596,8 +613,8 @@ static int __init i2c_imx_probe(struct platform_device *pdev) i2c_imx_set_clk(i2c_imx, bitrate); /* Set up chip registers to defaults */ - imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); - imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); + imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE ^ I2CR_IEN, i2c_imx, IMX_I2C_I2CR); + imx_i2c_write_reg(IMX_I2SR_CLR_OPCODE, i2c_imx, IMX_I2C_I2SR); /* Add I2C adapter */ ret = i2c_add_numbered_adapter(&i2c_imx->adapter);