From patchwork Tue Mar 21 22:43:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julia Cartwright X-Patchwork-Id: 741775 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vnp2m0Hxpz9s3w for ; Wed, 22 Mar 2017 09:51:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933405AbdCUWvF (ORCPT ); Tue, 21 Mar 2017 18:51:05 -0400 Received: from mx0a-00010702.pphosted.com ([148.163.156.75]:54382 "EHLO mx0b-00010702.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933226AbdCUWvD (ORCPT ); Tue, 21 Mar 2017 18:51:03 -0400 Received: from pps.filterd (m0098781.ppops.net [127.0.0.1]) by mx0a-00010702.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v2LMUXVE014921; Tue, 21 Mar 2017 17:43:14 -0500 Received: from ni.com (skprod2.natinst.com [130.164.80.23]) by mx0a-00010702.pphosted.com with ESMTP id 29baw40fmf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 21 Mar 2017 17:43:14 -0500 Received: from us-aus-exch2.ni.corp.natinst.com (us-aus-exch2.ni.corp.natinst.com [130.164.68.12]) by us-aus-skprod2.natinst.com (8.16.0.17/8.16.0.17) with ESMTPS id v2LMhDwb032571 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 21 Mar 2017 17:43:13 -0500 Received: from us-aus-exch5.ni.corp.natinst.com (130.164.68.15) by us-aus-exch2.ni.corp.natinst.com (130.164.68.12) with Microsoft SMTP Server (TLS) id 15.0.1156.6; Tue, 21 Mar 2017 17:43:13 -0500 Received: from us-aus-exhub2.ni.corp.natinst.com (130.164.68.32) by us-aus-exch5.ni.corp.natinst.com (130.164.68.15) with Microsoft SMTP Server (TLS) id 15.0.1156.6; Tue, 21 Mar 2017 17:43:13 -0500 Received: from jcartwri.amer.corp.natinst.com (130.164.49.7) by us-aus-exhub2.ni.corp.natinst.com (130.164.68.32) with Microsoft SMTP Server id 15.0.1156.6 via Frontend Transport; Tue, 21 Mar 2017 17:43:13 -0500 Received: by jcartwri.amer.corp.natinst.com (Postfix, from userid 1000) id 22ED03000E8; Tue, 21 Mar 2017 17:43:13 -0500 (CDT) From: Julia Cartwright To: William Breathitt Gray , Linus Walleij , Alexandre Courbot CC: , , Subject: [PATCH v2 9/9] gpio: pci-idio-16: make use of raw_spinlock variants Date: Tue, 21 Mar 2017 17:43:09 -0500 Message-ID: X-Mailer: git-send-email 2.12.0 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-21_20:, , signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703210190 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-21_20:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_policy_notspam policy=outbound_policy score=30 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=30 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703210190 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The pci-idio-16 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright Acked-by: William Breathitt Gray --- New patch as of v2 of series. drivers/gpio/gpio-pci-idio-16.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio-pci-idio-16.c b/drivers/gpio/gpio-pci-idio-16.c index 269ab628634b..7de4f6a2cb49 100644 --- a/drivers/gpio/gpio-pci-idio-16.c +++ b/drivers/gpio/gpio-pci-idio-16.c @@ -59,7 +59,7 @@ struct idio_16_gpio_reg { */ struct idio_16_gpio { struct gpio_chip chip; - spinlock_t lock; + raw_spinlock_t lock; struct idio_16_gpio_reg __iomem *reg; unsigned long irq_mask; }; @@ -121,7 +121,7 @@ static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset, } else base = &idio16gpio->reg->out0_7; - spin_lock_irqsave(&idio16gpio->lock, flags); + raw_spin_lock_irqsave(&idio16gpio->lock, flags); if (value) out_state = ioread8(base) | mask; @@ -130,7 +130,7 @@ static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset, iowrite8(out_state, base); - spin_unlock_irqrestore(&idio16gpio->lock, flags); + raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } static void idio_16_gpio_set_multiple(struct gpio_chip *chip, @@ -140,7 +140,7 @@ static void idio_16_gpio_set_multiple(struct gpio_chip *chip, unsigned long flags; unsigned int out_state; - spin_lock_irqsave(&idio16gpio->lock, flags); + raw_spin_lock_irqsave(&idio16gpio->lock, flags); /* process output lines 0-7 */ if (*mask & 0xFF) { @@ -160,7 +160,7 @@ static void idio_16_gpio_set_multiple(struct gpio_chip *chip, iowrite8(out_state, &idio16gpio->reg->out8_15); } - spin_unlock_irqrestore(&idio16gpio->lock, flags); + raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } static void idio_16_irq_ack(struct irq_data *data) @@ -177,11 +177,11 @@ static void idio_16_irq_mask(struct irq_data *data) idio16gpio->irq_mask &= ~mask; if (!idio16gpio->irq_mask) { - spin_lock_irqsave(&idio16gpio->lock, flags); + raw_spin_lock_irqsave(&idio16gpio->lock, flags); iowrite8(0, &idio16gpio->reg->irq_ctl); - spin_unlock_irqrestore(&idio16gpio->lock, flags); + raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } } @@ -196,11 +196,11 @@ static void idio_16_irq_unmask(struct irq_data *data) idio16gpio->irq_mask |= mask; if (!prev_irq_mask) { - spin_lock_irqsave(&idio16gpio->lock, flags); + raw_spin_lock_irqsave(&idio16gpio->lock, flags); ioread8(&idio16gpio->reg->irq_ctl); - spin_unlock_irqrestore(&idio16gpio->lock, flags); + raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } } @@ -229,11 +229,11 @@ static irqreturn_t idio_16_irq_handler(int irq, void *dev_id) struct gpio_chip *const chip = &idio16gpio->chip; int gpio; - spin_lock(&idio16gpio->lock); + raw_spin_lock(&idio16gpio->lock); irq_status = ioread8(&idio16gpio->reg->irq_status); - spin_unlock(&idio16gpio->lock); + raw_spin_unlock(&idio16gpio->lock); /* Make sure our device generated IRQ */ if (!(irq_status & 0x3) || !(irq_status & 0x4)) @@ -242,12 +242,12 @@ static irqreturn_t idio_16_irq_handler(int irq, void *dev_id) for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio) generic_handle_irq(irq_find_mapping(chip->irqdomain, gpio)); - spin_lock(&idio16gpio->lock); + raw_spin_lock(&idio16gpio->lock); /* Clear interrupt */ iowrite8(0, &idio16gpio->reg->in0_7); - spin_unlock(&idio16gpio->lock); + raw_spin_unlock(&idio16gpio->lock); return IRQ_HANDLED; } @@ -302,7 +302,7 @@ static int idio_16_probe(struct pci_dev *pdev, const struct pci_device_id *id) idio16gpio->chip.set = idio_16_gpio_set; idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple; - spin_lock_init(&idio16gpio->lock); + raw_spin_lock_init(&idio16gpio->lock); err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio); if (err) {