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d="scan'208";a="37119687" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 29 May 2024 09:46:56 +0200 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EB9CF1653B0; Wed, 29 May 2024 09:46:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1716968812; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=5mC5a04FWitjLLcuwOIE5BRImolQeptkvJ2oDOnHWlM=; b=Vq82qAAmpxXLhcHuuQtM4yvxWQ54zcTutca/XiOKmFTm75q1D+oLQjX7Sl5Q5uLjJAuyDz jO1JJr40afhDfyuYi8xrIYjSTrI4UqLTrkqWuVbdEeNc7MykT0CxwVKtr80DG9M5Bw0L/d qbM0e9/WJAHaZFrBKiSsgd2QXxU5khzSy+wG+n4EIOqskqwdv5F8dl9SmEwhSOquJ0MW1b pDwlcH/+goOpxP5keFAHEWZtANdHKV4ilEltYErNaH8k+VVrnlyX8VHZtJb6ovvE7pedUJ bW1jIa2psCM3Kf8Y8fBmURGoh/H5LKC0rzrv7D4TT8BRPK7ZQkr5uBC71FO3Ig== From: Matthias Schiffer To: Linus Walleij , Bartosz Golaszewski Cc: Andrew Lunn , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Gregor Herburger , linux@ew.tq-group.com, Matthias Schiffer Subject: [PATCH 6/8] gpio: tqmx86: store IRQ triggers without offsetting index Date: Wed, 29 May 2024 09:45:18 +0200 Message-ID: <9525c437801bbb9be1c67745a0ffb7797bb58e05.1716967982.git.matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 This will allow us to move all offset handling into a single place in the following commits. The additional irq_type indices remain unused, but the tqmx86_gpio_data size increase is insignificant. No functional change intended. Fixes: b868db94a6a7 ("gpio: tqmx86: Add GPIO from for this IO controller") Signed-off-by: Matthias Schiffer --- drivers/gpio/gpio-tqmx86.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index d6e77f604f4df..4b37cc3bdd455 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -44,7 +44,7 @@ struct tqmx86_gpio_data { int irq; raw_spinlock_t spinlock; DECLARE_BITMAP(output, TQMX86_NGPIO); - u8 irq_type[TQMX86_NGPI]; + u8 irq_type[TQMX86_NGPIO]; }; static u8 tqmx86_gpio_read(struct tqmx86_gpio_data *gd, unsigned int reg) @@ -146,7 +146,7 @@ static void tqmx86_gpio_irq_unmask(struct irq_data *data) gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(data)); mask = TQMX86_GPII_MASK(offset); - val = TQMX86_GPII_CONFIG(offset, gpio->irq_type[offset]); + val = TQMX86_GPII_CONFIG(offset, gpio->irq_type[data->hwirq]); raw_spin_lock_irqsave(&gpio->spinlock, flags); _tqmx86_gpio_update_bits(gpio, TQMX86_GPIIC, mask, val); raw_spin_unlock_irqrestore(&gpio->spinlock, flags); @@ -175,7 +175,7 @@ static int tqmx86_gpio_irq_set_type(struct irq_data *data, unsigned int type) return -EINVAL; /* not supported */ } - gpio->irq_type[offset] = new_type; + gpio->irq_type[data->hwirq] = new_type; mask = TQMX86_GPII_MASK(offset); val = TQMX86_GPII_CONFIG(offset, new_type);