From patchwork Thu Mar 9 16:22:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julia Cartwright X-Patchwork-Id: 737069 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vfH4v2J6Nz9rxl for ; Fri, 10 Mar 2017 04:12:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932275AbdCIRLB (ORCPT ); Thu, 9 Mar 2017 12:11:01 -0500 Received: from mx0a-00010702.pphosted.com ([148.163.156.75]:50170 "EHLO mx0b-00010702.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754526AbdCIRK7 (ORCPT ); Thu, 9 Mar 2017 12:10:59 -0500 Received: from pps.filterd (m0098781.ppops.net [127.0.0.1]) by mx0a-00010702.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v29GKr65006323; Thu, 9 Mar 2017 10:22:15 -0600 Received: from ni.com (skprod2.natinst.com [130.164.80.23]) by mx0a-00010702.pphosted.com with ESMTP id 292xcdtfju-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Mar 2017 10:22:15 -0600 Received: from us-aus-exch2.ni.corp.natinst.com (us-aus-exch2.ni.corp.natinst.com [130.164.68.12]) by us-aus-skprod2.natinst.com (8.16.0.17/8.16.0.17) with ESMTPS id v29GMDUb008773 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 9 Mar 2017 10:22:14 -0600 Received: from us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) by us-aus-exch2.ni.corp.natinst.com (130.164.68.12) with Microsoft SMTP Server (TLS) id 15.0.1156.6; Thu, 9 Mar 2017 10:22:14 -0600 Received: from jcartwri.amer.corp.natinst.com (130.164.49.7) by us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) with Microsoft SMTP Server id 15.0.1156.6 via Frontend Transport; Thu, 9 Mar 2017 10:22:14 -0600 Received: by jcartwri.amer.corp.natinst.com (Postfix, from userid 1000) id 3291930111D; Thu, 9 Mar 2017 10:22:14 -0600 (CST) From: Julia Cartwright To: Linus Walleij , Maxime Ripard , Chen-Yu Tsai CC: , Thomas Gleixner , , Subject: [PATCH 19/19] pinctrl: sunxi: make use of raw_spinlock variants Date: Thu, 9 Mar 2017 10:22:06 -0600 Message-ID: <6b509f22ec93562892e787507e62137cee7c9114.1489015238.git.julia@ni.com> X-Mailer: git-send-email 2.11.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-09_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-09_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=30 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=30 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The sunxi pinctrl driver currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright --- drivers/pinctrl/sunxi/pinctrl-sunxi.c | 26 +++++++++++++------------- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 60e6e36c4a7e..58774acfc814 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -581,11 +581,11 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, return -ENOTSUPP; } - spin_lock_irqsave(&pctl->lock, flags); + raw_spin_lock_irqsave(&pctl->lock, flags); reg = readl(pctl->membase + offset); reg &= ~(mask << shift); writel(reg | val << shift, pctl->membase + offset); - spin_unlock_irqrestore(&pctl->lock, flags); + raw_spin_unlock_irqrestore(&pctl->lock, flags); } /* for each config */ return 0; @@ -634,7 +634,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev, unsigned long flags; u32 val, mask; - spin_lock_irqsave(&pctl->lock, flags); + raw_spin_lock_irqsave(&pctl->lock, flags); pin -= pctl->desc->pin_base; val = readl(pctl->membase + sunxi_mux_reg(pin)); @@ -642,7 +642,7 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev, writel((val & ~mask) | config << sunxi_mux_offset(pin), pctl->membase + sunxi_mux_reg(pin)); - spin_unlock_irqrestore(&pctl->lock, flags); + raw_spin_unlock_irqrestore(&pctl->lock, flags); } static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, @@ -733,7 +733,7 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, unsigned long flags; u32 regval; - spin_lock_irqsave(&pctl->lock, flags); + raw_spin_lock_irqsave(&pctl->lock, flags); regval = readl(pctl->membase + reg); @@ -744,7 +744,7 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, writel(regval, pctl->membase + reg); - spin_unlock_irqrestore(&pctl->lock, flags); + raw_spin_unlock_irqrestore(&pctl->lock, flags); } static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, @@ -856,7 +856,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) return -EINVAL; } - spin_lock_irqsave(&pctl->lock, flags); + raw_spin_lock_irqsave(&pctl->lock, flags); if (type & IRQ_TYPE_LEVEL_MASK) irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, @@ -869,7 +869,7 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) regval &= ~(IRQ_CFG_IRQ_MASK << index); writel(regval | (mode << index), pctl->membase + reg); - spin_unlock_irqrestore(&pctl->lock, flags); + raw_spin_unlock_irqrestore(&pctl->lock, flags); return 0; } @@ -893,13 +893,13 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d) unsigned long flags; u32 val; - spin_lock_irqsave(&pctl->lock, flags); + raw_spin_lock_irqsave(&pctl->lock, flags); /* Mask the IRQ */ val = readl(pctl->membase + reg); writel(val & ~(1 << idx), pctl->membase + reg); - spin_unlock_irqrestore(&pctl->lock, flags); + raw_spin_unlock_irqrestore(&pctl->lock, flags); } static void sunxi_pinctrl_irq_unmask(struct irq_data *d) @@ -910,13 +910,13 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d) unsigned long flags; u32 val; - spin_lock_irqsave(&pctl->lock, flags); + raw_spin_lock_irqsave(&pctl->lock, flags); /* Unmask the IRQ */ val = readl(pctl->membase + reg); writel(val | (1 << idx), pctl->membase + reg); - spin_unlock_irqrestore(&pctl->lock, flags); + raw_spin_unlock_irqrestore(&pctl->lock, flags); } static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) @@ -1253,7 +1253,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, return -ENOMEM; platform_set_drvdata(pdev, pctl); - spin_lock_init(&pctl->lock); + raw_spin_lock_init(&pctl->lock); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pctl->membase = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index e1aedd260b2e..a9d315a1256c 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -134,7 +134,7 @@ struct sunxi_pinctrl { unsigned ngroups; int *irq; unsigned *irq_array; - spinlock_t lock; + raw_spinlock_t lock; struct pinctrl_dev *pctl_dev; unsigned long variant; };