From patchwork Thu Mar 9 16:21:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julia Cartwright X-Patchwork-Id: 737060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vfGj26Vmsz9s7Z for ; Fri, 10 Mar 2017 03:55:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932638AbdCIQzB (ORCPT ); Thu, 9 Mar 2017 11:55:01 -0500 Received: from mx0a-00010702.pphosted.com ([148.163.156.75]:47597 "EHLO mx0b-00010702.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932635AbdCIQzA (ORCPT ); Thu, 9 Mar 2017 11:55:00 -0500 Received: from pps.filterd (m0098781.ppops.net [127.0.0.1]) by mx0a-00010702.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v29GKr62006323; Thu, 9 Mar 2017 10:22:12 -0600 Received: from ni.com (skprod3.natinst.com [130.164.80.24]) by mx0a-00010702.pphosted.com with ESMTP id 292xcdtfjg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Mar 2017 10:22:12 -0600 Received: from us-aus-exhub2.ni.corp.natinst.com (us-aus-exhub2.ni.corp.natinst.com [130.164.68.32]) by us-aus-skprod3.natinst.com (8.16.0.17/8.16.0.17) with ESMTPS id v29GMBOn008892 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 9 Mar 2017 10:22:11 -0600 Received: from us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) by us-aus-exhub2.ni.corp.natinst.com (130.164.68.32) with Microsoft SMTP Server (TLS) id 15.0.1156.6; Thu, 9 Mar 2017 10:22:10 -0600 Received: from jcartwri.amer.corp.natinst.com (130.164.49.7) by us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) with Microsoft SMTP Server id 15.0.1156.6 via Frontend Transport; Thu, 9 Mar 2017 10:22:10 -0600 Received: by jcartwri.amer.corp.natinst.com (Postfix, from userid 1000) id F0A9230111D; Thu, 9 Mar 2017 10:22:10 -0600 (CST) From: Julia Cartwright To: Linus Walleij , Alexandre Courbot CC: , Thomas Gleixner , Subject: [PATCH 11/19] gpio: zx: make use of raw_spinlock variants Date: Thu, 9 Mar 2017 10:21:58 -0600 Message-ID: <5198486738fd89f8187b911256ddd3f09a7f9188.1489015238.git.julia@ni.com> X-Mailer: git-send-email 2.11.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-09_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 suspectscore=2 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-09_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=30 priorityscore=1501 malwarescore=0 suspectscore=8 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=30 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The zx gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright --- drivers/gpio/gpio-zx.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpio-zx.c b/drivers/gpio/gpio-zx.c index 93de8be0d885..be3a87da8438 100644 --- a/drivers/gpio/gpio-zx.c +++ b/drivers/gpio/gpio-zx.c @@ -41,7 +41,7 @@ #define ZX_GPIO_NR 16 struct zx_gpio { - spinlock_t lock; + raw_spinlock_t lock; void __iomem *base; struct gpio_chip gc; @@ -56,11 +56,11 @@ static int zx_direction_input(struct gpio_chip *gc, unsigned offset) if (offset >= gc->ngpio) return -EINVAL; - spin_lock_irqsave(&chip->lock, flags); + raw_spin_lock_irqsave(&chip->lock, flags); gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); gpiodir &= ~BIT(offset); writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); - spin_unlock_irqrestore(&chip->lock, flags); + raw_spin_unlock_irqrestore(&chip->lock, flags); return 0; } @@ -75,7 +75,7 @@ static int zx_direction_output(struct gpio_chip *gc, unsigned offset, if (offset >= gc->ngpio) return -EINVAL; - spin_lock_irqsave(&chip->lock, flags); + raw_spin_lock_irqsave(&chip->lock, flags); gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); gpiodir |= BIT(offset); writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); @@ -84,7 +84,7 @@ static int zx_direction_output(struct gpio_chip *gc, unsigned offset, writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1); else writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0); - spin_unlock_irqrestore(&chip->lock, flags); + raw_spin_unlock_irqrestore(&chip->lock, flags); return 0; } @@ -118,7 +118,7 @@ static int zx_irq_type(struct irq_data *d, unsigned trigger) if (offset < 0 || offset >= ZX_GPIO_NR) return -EINVAL; - spin_lock_irqsave(&chip->lock, flags); + raw_spin_lock_irqsave(&chip->lock, flags); gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV); gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE); @@ -151,7 +151,7 @@ static int zx_irq_type(struct irq_data *d, unsigned trigger) writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP); writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN); writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV); - spin_unlock_irqrestore(&chip->lock, flags); + raw_spin_unlock_irqrestore(&chip->lock, flags); return 0; } @@ -184,12 +184,12 @@ static void zx_irq_mask(struct irq_data *d) u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR); u16 gpioie; - spin_lock(&chip->lock); + raw_spin_lock(&chip->lock); gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask; writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask; writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); - spin_unlock(&chip->lock); + raw_spin_unlock(&chip->lock); } static void zx_irq_unmask(struct irq_data *d) @@ -199,12 +199,12 @@ static void zx_irq_unmask(struct irq_data *d) u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR); u16 gpioie; - spin_lock(&chip->lock); + raw_spin_lock(&chip->lock); gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask; writew_relaxed(gpioie, chip->base + ZX_GPIO_IM); gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask; writew_relaxed(gpioie, chip->base + ZX_GPIO_IE); - spin_unlock(&chip->lock); + raw_spin_unlock(&chip->lock); } static struct irq_chip zx_irqchip = { @@ -230,7 +230,7 @@ static int zx_gpio_probe(struct platform_device *pdev) if (IS_ERR(chip->base)) return PTR_ERR(chip->base); - spin_lock_init(&chip->lock); + raw_spin_lock_init(&chip->lock); if (of_property_read_bool(dev->of_node, "gpio-ranges")) { chip->gc.request = gpiochip_generic_request; chip->gc.free = gpiochip_generic_free;