From patchwork Thu Jun 4 23:31:49 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 480925 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 66ACA14016A for ; Fri, 5 Jun 2015 09:31:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752508AbbFDXbx (ORCPT ); Thu, 4 Jun 2015 19:31:53 -0400 Received: from mail-la0-f49.google.com ([209.85.215.49]:35835 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752335AbbFDXbx (ORCPT ); Thu, 4 Jun 2015 19:31:53 -0400 Received: by labko7 with SMTP id ko7so42736078lab.2 for ; Thu, 04 Jun 2015 16:31:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding:content-type; bh=T+pd43dw7VOYLpkJQ1fX32QFv+evnQE1D4+a5qxXN1s=; b=KMvZ+psq0xqx+Zupng0/vSydWg9p4Oe+0VzLVO2p6I05B/Mnj8GHVh/94mAhKKDBGF g+elFvLN/CXY/y6cPDBnP3HuucH8uKcD6MbEtNSvraQ7V+obYguoQ6Y9kaBV02JT6h12 25l6s22azR2bSOjPbzPqkgXlV/Gfh0Ld3Q9kXJ9+HrJqrsYHXud0jR1s1PiefJeuK95z XK2g3lFev0FLZSQ+NGThJ4kSz0l5ZVtDz7IeIBv1d6xvs46l2rvCnDsj4EMWjbGu129V mCIWPFMxow13BcxZM1lH4V6I5PvAX8iDU/dpSFNmA+dhvApf39ElYwLAjPKFV0Skaaeh ah7g== X-Gm-Message-State: ALoCoQmk7mOkH9sv67OetwmTm1SfZL664oOGEIdmIGT68Y2xrVHPL1rl2+7IRdzFwCMXRTXSTaQa X-Received: by 10.112.156.231 with SMTP id wh7mr463136lbb.118.1433460711777; Thu, 04 Jun 2015 16:31:51 -0700 (PDT) Received: from wasted.cogentembedded.com (ppp85-141-196-196.pppoe.mtu-net.ru. [85.141.196.196]) by mx.google.com with ESMTPSA id yc3sm1181539lbb.6.2015.06.04.16.31.50 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Jun 2015 16:31:50 -0700 (PDT) From: Sergei Shtylyov To: linus.walleij@linaro.org, linux-sh@vger.kernel.org, laurent.pinchart@ideasonboard.com, linux-gpio@vger.kernel.org Subject: [PATCH v2 4/4] sh-pfc: r8a7791 remove non-existing GPIO pins Date: Fri, 05 Jun 2015 02:31:49 +0300 Message-ID: <38751183.VIdH0V180E@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.7 (Linux/3.19.8-100.fc20.x86_64; KDE/4.14.7; x86_64; ; ) In-Reply-To: <4326653.qPvIJDU6F2@wasted.cogentembedded.com> References: <4326653.qPvIJDU6F2@wasted.cogentembedded.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Laurent Pinchart GPIO banks 1 and 7 are missing pins 26 to 31. Remove them. Signed-off-by: Laurent Pinchart Signed-off-by: Sergei Shtylyov --- Changes in version 2: - renamed the patch. drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -14,15 +14,30 @@ #include "core.h" #include "sh_pfc.h" +#define PORT_GP_26(bank, fn, sfx) \ + PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \ + PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \ + PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \ + PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \ + PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \ + PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \ + PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \ + PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \ + PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \ + PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \ + PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \ + PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \ + PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx) + #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ + PORT_GP_26(1, fn, sfx), \ PORT_GP_32(2, fn, sfx), \ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx), \ PORT_GP_32(6, fn, sfx), \ - PORT_GP_32(7, fn, sfx) + PORT_GP_26(7, fn, sfx) enum { PINMUX_RESERVED = 0,