| Message ID | 20240902072859.583490-1-patrick.rudolph@9elements.com |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: pinctrl-cy8c95x0: Fix regcache | expand |
On Mon, Sep 2, 2024 at 10:30 AM Patrick Rudolph <patrick.rudolph@9elements.com> wrote: > > The size of the mux stride was of by one, which could result in off > invalid pin configuration on the device side or invalid state > readings on the software side. > > While on it also update the code and: > - Increase the mux stride size to 16 > - Align the virtual muxed regmap range to 16 > - Start the regmap window at the selector > - Mark reserved registers as not-readable Reported-by: Andy Shevchenko <andy@kernel.org> Reviewed-by: Andy Shevchenko <andy@kernel.org> ... > - if (reg >= CY8C95X0_VIRTUAL) > + if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) < 12) Probably good to have 12 defined, but also a comment suffice, like: /* Only 12 registers are present per port (see Table 6 in the datasheet). */ > return true;
On Mon, Sep 2, 2024 at 9:30 AM Patrick Rudolph <patrick.rudolph@9elements.com> wrote: > The size of the mux stride was of by one, which could result in > invalid pin configuration on the device side or invalid state > readings on the software side. > > While on it also update the code and: > - Increase the mux stride size to 16 > - Align the virtual muxed regmap range to 16 > - Start the regmap window at the selector > - Mark reserved registers as not-readable > > Fixes: 8670de9fae49 ("pinctrl: cy8c95x0: Use regmap ranges") > Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> I was waiting for a follow-up fixing Andy's small remarks but now I just applied this and fixed up the nits myself. Yours, Linus Walleij
diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 9a92707d2525..21e9e7b264c8 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -62,11 +62,11 @@ #define MAX_BANK 8 #define BANK_SZ 8 #define MAX_LINE (MAX_BANK * BANK_SZ) -#define MUXED_STRIDE (CY8C95X0_DRV_HIZ - CY8C95X0_INTMASK) +#define MUXED_STRIDE 16 #define CY8C95X0_GPIO_MASK GENMASK(7, 0) -#define CY8C95X0_VIRTUAL (CY8C95X0_COMMAND + 1) +#define CY8C95X0_VIRTUAL 0x40 #define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \ - (CY8C95X0_VIRTUAL + (x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE) + (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE) static const struct i2c_device_id cy8c95x0_id[] = { { "cy8c9520", 20, }, @@ -329,7 +329,7 @@ static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin) static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg) { - if (reg >= CY8C95X0_VIRTUAL) + if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) < 12) return true; switch (reg) { @@ -444,7 +444,7 @@ static const struct regmap_range_cfg cy8c95x0_ranges[] = { .selector_reg = CY8C95X0_PORTSEL, .selector_mask = 0x07, .selector_shift = 0x0, - .window_start = CY8C95X0_INTMASK, + .window_start = CY8C95X0_PORTSEL, .window_len = MUXED_STRIDE, } };
The size of the mux stride was of by one, which could result in invalid pin configuration on the device side or invalid state readings on the software side. While on it also update the code and: - Increase the mux stride size to 16 - Align the virtual muxed regmap range to 16 - Start the regmap window at the selector - Mark reserved registers as not-readable Fixes: 8670de9fae49 ("pinctrl: cy8c95x0: Use regmap ranges") Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> --- drivers/pinctrl/pinctrl-cy8c95x0.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)