Message ID | 20240711193749.2397471-4-tmaimon77@gmail.com |
---|---|
State | New |
Headers | show
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Fri, 12 Jul 2024 03:37:57 +0800 Received: from taln58.nuvoton.co.il (10.191.1.178) by NTHCCAS01.nuvoton.com (10.1.8.28) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Fri, 12 Jul 2024 03:37:57 +0800 Received: from taln60.nuvoton.co.il (taln60 [10.191.1.180]) by taln58.nuvoton.co.il (Postfix) with ESMTP id 08FC65F676; Thu, 11 Jul 2024 22:37:56 +0300 (IDT) Received: by taln60.nuvoton.co.il (Postfix, from userid 10070) id 090DFDC0F7F; Thu, 11 Jul 2024 22:37:56 +0300 (IDT) From: Tomer Maimon <tmaimon77@gmail.com> To: <linus.walleij@linaro.org>, <avifishman70@gmail.com>, <tali.perry1@gmail.com>, <joel@jms.id.au>, <venture@google.com>, <yuenn@google.com>, <benjaminfair@google.com> CC: <openbmc@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>, <linux-gpio@vger.kernel.org>, Tomer Maimon <tmaimon77@gmail.com> Subject: [PATCH v1 3/7] pinctrl: nuvoton: npcm8xx: add pin 250 to DDR pins group Date: Thu, 11 Jul 2024 22:37:45 +0300 Message-ID: <20240711193749.2397471-4-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240711193749.2397471-1-tmaimon77@gmail.com> References: <20240711193749.2397471-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: <linux-gpio.vger.kernel.org> List-Subscribe: <mailto:linux-gpio+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-gpio+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NotSetDelaration: True X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: HK3PEPF0000021E:EE_|SEZPR03MB8568:EE_ X-MS-Office365-Filtering-Correlation-Id: 7dfc9074-4db9-4001-7546-08dca1e0f88d X-MS-Exchange-SenderADCheck: 2 X-MS-Exchange-AntiSpam-Relay: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|7093399012|35950700016|48200799018|61400799027|35450700002; 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pinctrl: npcm8xx: pin configuration changes
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diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index cf021d0e8099..f342aec3f6ca 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -516,7 +516,7 @@ static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, static const int rg2mdio_pins[] = { 216, 217 }; static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, - 213, 214, 215, 216, 217 }; + 213, 214, 215, 216, 217, 250 }; static const int iox1_pins[] = { 0, 1, 2, 3 }; static const int iox2_pins[] = { 4, 5, 6, 7 }; @@ -1570,6 +1570,7 @@ static const struct npcm8xx_pincfg pincfg[] = { NPCM8XX_PINCFG(245, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(246, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(247, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(250, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM8XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ NPCM8XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */
Add pin 250 to DDR pins group on the Nuvoton NPCM8xx BMC SoC. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> --- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)