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Sat, 6 Apr 2024 12:37:22 +0000 (UTC) Received: from localhost.localdomain (unknown [10.39.192.50]) by smtp.corp.redhat.com (Postfix) with ESMTP id 83250C04120; Sat, 6 Apr 2024 12:37:21 +0000 (UTC) From: Hans de Goede To: Mika Westerberg , Andy Shevchenko , Linus Walleij Cc: Hans de Goede , linux-gpio@vger.kernel.org Subject: [PATCH 2/2] pinctrl: baytrail: Add pinconf group for uart3 Date: Sat, 6 Apr 2024 14:35:06 +0200 Message-ID: <20240406123506.12078-2-hdegoede@redhat.com> In-Reply-To: <20240406123506.12078-1-hdegoede@redhat.com> References: <20240406123506.12078-1-hdegoede@redhat.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.8 GPIO_S0_SC57 / GPIO_S0_SC61 can be muxed to PCU_UART_TXD / PCU_UART_RXD, add a pinconf group for this. On Bay Trail board schematics using these pins as UART these are called UART3_TXD / UART3_RXD, name the pinconf group "uart3_grp" to be consistent with the schematics. Signed-off-by: Hans de Goede --- drivers/pinctrl/intel/pinctrl-baytrail.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 019a886a37ae..bd2363355a60 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -231,6 +231,7 @@ static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { /* SCORE groups */ static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; +static const unsigned int byt_score_uart3_pins[] = { 57, 61 }; static const unsigned int byt_score_pwm0_pins[] = { 94 }; static const unsigned int byt_score_pwm1_pins[] = { 95 }; @@ -282,6 +283,8 @@ static const struct intel_pingroup byt_score_groups[] = { PIN_GROUP("uart1_grp_gpio", byt_score_uart1_pins, 0), PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1), PIN_GROUP("uart2_grp_gpio", byt_score_uart2_pins, 0), + PIN_GROUP("uart3_grp", byt_score_uart3_pins, 1), + PIN_GROUP("uart3_grp_gpio", byt_score_uart3_pins, 0), PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1), PIN_GROUP("pwm0_grp_gpio", byt_score_pwm0_pins, 0), PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1), @@ -335,7 +338,7 @@ static const struct intel_pingroup byt_score_groups[] = { }; static const char * const byt_score_uart_groups[] = { - "uart1_grp", "uart2_grp", + "uart1_grp", "uart2_grp", "uart3_grp", }; static const char * const byt_score_pwm_groups[] = { "pwm0_grp", "pwm1_grp", @@ -359,7 +362,7 @@ static const char * const byt_score_plt_clk_groups[] = { }; static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; static const char * const byt_score_gpio_groups[] = { - "uart1_grp_gpio", "uart2_grp_gpio", "pwm0_grp_gpio", + "uart1_grp_gpio", "uart2_grp_gpio", "uart3_grp_gpio", "pwm0_grp_gpio", "pwm1_grp_gpio", "ssp0_grp_gpio", "ssp1_grp_gpio", "ssp2_grp_gpio", "sio_spi_grp_gpio", "i2c0_grp_gpio", "i2c1_grp_gpio", "i2c2_grp_gpio", "i2c3_grp_gpio", "i2c4_grp_gpio", "i2c5_grp_gpio", "i2c6_grp_gpio",