| Message ID | 20230203165054.390762-1-krzysztof.kozlowski@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: qcom: sm8450-lpass-lpi: correct swr_rx_data group | expand |
On 3.02.2023 17:50, Krzysztof Kozlowski wrote: > According to hardware programming guide, the swr_rx_data pin group has > only two pins (GPIO5 and GPIO6). This is also visible in "struct > sm8450_groups" in the driver - GPIO15 does not have swr_rx_data > function. > > Fixes: ec1652fc4d56 ("pinctrl: qcom: Add sm8450 lpass lpi pinctrl driver") > Cc: <stable@vger.kernel.org> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c > index c3c8c34148f1..e22d03ce292e 100644 > --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c > +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c > @@ -105,7 +105,7 @@ static const struct pinctrl_pin_desc sm8450_lpi_pins[] = { > static const char * const swr_tx_clk_groups[] = { "gpio0" }; > static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; > static const char * const swr_rx_clk_groups[] = { "gpio3" }; > -static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5", "gpio15" }; > +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; > static const char * const dmic1_clk_groups[] = { "gpio6" }; > static const char * const dmic1_data_groups[] = { "gpio7" }; > static const char * const dmic2_clk_groups[] = { "gpio8" };
On Fri, Feb 3, 2023 at 5:51 PM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > According to hardware programming guide, the swr_rx_data pin group has > only two pins (GPIO5 and GPIO6). This is also visible in "struct > sm8450_groups" in the driver - GPIO15 does not have swr_rx_data > function. > > Fixes: ec1652fc4d56 ("pinctrl: qcom: Add sm8450 lpass lpi pinctrl driver") > Cc: <stable@vger.kernel.org> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patch applied for (last minute) fixes! Yours, Linus Walleij
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c index c3c8c34148f1..e22d03ce292e 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -105,7 +105,7 @@ static const struct pinctrl_pin_desc sm8450_lpi_pins[] = { static const char * const swr_tx_clk_groups[] = { "gpio0" }; static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio14" }; static const char * const swr_rx_clk_groups[] = { "gpio3" }; -static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5", "gpio15" }; +static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; static const char * const dmic1_clk_groups[] = { "gpio6" }; static const char * const dmic1_data_groups[] = { "gpio7" }; static const char * const dmic2_clk_groups[] = { "gpio8" };
According to hardware programming guide, the swr_rx_data pin group has only two pins (GPIO5 and GPIO6). This is also visible in "struct sm8450_groups" in the driver - GPIO15 does not have swr_rx_data function. Fixes: ec1652fc4d56 ("pinctrl: qcom: Add sm8450 lpass lpi pinctrl driver") Cc: <stable@vger.kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)