diff mbox series

[v2,9/9] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}

Message ID 20221221000242.340202-10-prabhakar.mahadev-lad.rj@bp.renesas.com
State New
Headers show
Series Add IRQC support to RZ/G2UL SoC | expand

Commit Message

Lad, Prabhakar Dec. 21, 2022, 12:02 a.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
ETH1 respectively.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1 -> v2
* No change
---
 arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

Comments

Geert Uytterhoeven Dec. 27, 2022, 1:02 p.m. UTC | #1 
Hi Prabhakar,

On Wed, Dec 21, 2022 at 1:04 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
> ETH1 respectively.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> @@ -6,6 +6,7 @@
>   */
>
>  #include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
>  #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
>
>  / {
> @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
>                 compatible = "ethernet-phy-id0022.1640",
>                              "ethernet-phy-ieee802.3-c22";
>                 reg = <7>;
> +               interrupt-parent = <&irqc>;

Note that arch/riscv/boot/dts/renesas/r9a07g043f.dtsi does not have
the irqc node yet, so I cannot take this as-is.

> +               interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
>                 rxc-skew-psec = <2400>;
>                 txc-skew-psec = <2400>;
>                 rxdv-skew-psec = <0>;

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
Lad, Prabhakar Dec. 28, 2022, 11:36 p.m. UTC | #2 
Hi Geert,

Thank you for the review.

On Tue, Dec 27, 2022 at 1:02 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Dec 21, 2022 at 1:04 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
> > ETH1 respectively.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
> > @@ -6,6 +6,7 @@
> >   */
> >
> >  #include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
> >  #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
> >
> >  / {
> > @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
> >                 compatible = "ethernet-phy-id0022.1640",
> >                              "ethernet-phy-ieee802.3-c22";
> >                 reg = <7>;
> > +               interrupt-parent = <&irqc>;
>
> Note that arch/riscv/boot/dts/renesas/r9a07g043f.dtsi does not have
> the irqc node yet, so I cannot take this as-is.
>
Agreed, is it OK if we temporarily add the (above+below) properties in
the boards DTS and once we have full fledged support for RZ/Five we
move it back to the SoM DTSi (as done in this patch)?

Cheers,
Prabhakar

> > +               interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
> >                 rxc-skew-psec = <2400>;
> >                 txc-skew-psec = <2400>;
> >                 rxdv-skew-psec = <0>;
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
index 931efc07d6fb..49ecd33aeeb8 100644
--- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -6,6 +6,7 @@ 
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
 / {
@@ -77,6 +78,8 @@  phy0: ethernet-phy@7 {
 		compatible = "ethernet-phy-id0022.1640",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <7>;
+		interrupt-parent = <&irqc>;
+		interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
 		rxc-skew-psec = <2400>;
 		txc-skew-psec = <2400>;
 		rxdv-skew-psec = <0>;
@@ -104,6 +107,8 @@  phy1: ethernet-phy@7 {
 		compatible = "ethernet-phy-id0022.1640",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <7>;
+		interrupt-parent = <&irqc>;
+		interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
 		rxc-skew-psec = <2400>;
 		txc-skew-psec = <2400>;
 		rxdv-skew-psec = <0>;
@@ -151,7 +156,8 @@  eth0_pins: eth0 {
 			 <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
 			 <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
 			 <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
-			 <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
+			 <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
+			 <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
 	};
 
 	eth1_pins: eth1 {
@@ -169,7 +175,8 @@  eth1_pins: eth1 {
 			 <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
 			 <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
 			 <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
-			 <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
+			 <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
+			 <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
 	};
 
 	sdhi0_emmc_pins: sd0emmc {