| Message ID | 20200913225005.30218-1-dmitry.baryshkov@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: qcom: sm8250: correct sdc2_clk and ngpios | expand |
On Sun 13 Sep 17:50 CDT 2020, Dmitry Baryshkov wrote: > Correct sdc2_clk pin definition (register offset) and ngpios (SM8250 has > 180 GPIO pins). > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Fixes: 4e3ec9e407ad5058003309072b37111f7b8c900a > --- > drivers/pinctrl/qcom/pinctrl-sm8250.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c > index a660f1274b66..4f7dae61b089 100644 > --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c > +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c > @@ -1308,7 +1308,7 @@ static const struct msm_pingroup sm8250_groups[] = { > [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), > [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), > [180] = UFS_RESET(ufs_reset, 0xb8000), > - [181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6), > + [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6), You're right. > [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), > [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), > }; > @@ -1320,7 +1320,7 @@ static const struct msm_pinctrl_soc_data sm8250_pinctrl = { > .nfunctions = ARRAY_SIZE(sm8250_functions), > .groups = sm8250_groups, > .ngroups = ARRAY_SIZE(sm8250_groups), > - .ngpios = 181, > + .ngpios = 180, But, while it is correct that SM8250 only has 180 GPIOs, we're exposing UFS_RESET as a gpio as well, so this should therefor be 181. Sorry for the obfuscation here... Regards, Bjorn > .tiles = sm8250_tiles, > .ntiles = ARRAY_SIZE(sm8250_tiles), > }; > -- > 2.28.0 >
Hello, On Mon, 14 Sep 2020 at 02:44, Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > On Sun 13 Sep 17:50 CDT 2020, Dmitry Baryshkov wrote: > > > Correct sdc2_clk pin definition (register offset) and ngpios (SM8250 has > > 180 GPIO pins). > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Fixes: 4e3ec9e407ad5058003309072b37111f7b8c900a > > --- > > drivers/pinctrl/qcom/pinctrl-sm8250.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c > > index a660f1274b66..4f7dae61b089 100644 > > --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c > > +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c > > @@ -1308,7 +1308,7 @@ static const struct msm_pingroup sm8250_groups[] = { > > [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), > > [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), > > [180] = UFS_RESET(ufs_reset, 0xb8000), > > - [181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6), > > + [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6), > > You're right. > > > [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), > > [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), > > }; > > @@ -1320,7 +1320,7 @@ static const struct msm_pinctrl_soc_data sm8250_pinctrl = { > > .nfunctions = ARRAY_SIZE(sm8250_functions), > > .groups = sm8250_groups, > > .ngroups = ARRAY_SIZE(sm8250_groups), > > - .ngpios = 181, > > + .ngpios = 180, > > But, while it is correct that SM8250 only has 180 GPIOs, we're exposing > UFS_RESET as a gpio as well, so this should therefor be 181. Sorry for > the obfuscation here... True. Could you please drop the second part of the patch on your own? Or would you prefer for me to send v2?
On Sun 13 Sep 18:52 CDT 2020, Dmitry Baryshkov wrote: > Hello, > > On Mon, 14 Sep 2020 at 02:44, Bjorn Andersson > <bjorn.andersson@linaro.org> wrote: > > > > On Sun 13 Sep 17:50 CDT 2020, Dmitry Baryshkov wrote: > > > > > Correct sdc2_clk pin definition (register offset) and ngpios (SM8250 has > > > 180 GPIO pins). > > > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > > Fixes: 4e3ec9e407ad5058003309072b37111f7b8c900a > > > --- > > > drivers/pinctrl/qcom/pinctrl-sm8250.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c > > > index a660f1274b66..4f7dae61b089 100644 > > > --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c > > > +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c > > > @@ -1308,7 +1308,7 @@ static const struct msm_pingroup sm8250_groups[] = { > > > [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), > > > [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), > > > [180] = UFS_RESET(ufs_reset, 0xb8000), > > > - [181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6), > > > + [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6), > > > > You're right. > > > > > [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), > > > [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), > > > }; > > > @@ -1320,7 +1320,7 @@ static const struct msm_pinctrl_soc_data sm8250_pinctrl = { > > > .nfunctions = ARRAY_SIZE(sm8250_functions), > > > .groups = sm8250_groups, > > > .ngroups = ARRAY_SIZE(sm8250_groups), > > > - .ngpios = 181, > > > + .ngpios = 180, > > > > But, while it is correct that SM8250 only has 180 GPIOs, we're exposing > > UFS_RESET as a gpio as well, so this should therefor be 181. Sorry for > > the obfuscation here... > > True. Could you please drop the second part of the patch on your own? > Or would you prefer for me to send v2? > This goes through Linus' tree, so it would be up to him. If you want to avoid waiting for his response go ahead and post a v2 - and I'll give you a r-b on it. Regards, Bjorn
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c index a660f1274b66..4f7dae61b089 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -1308,7 +1308,7 @@ static const struct msm_pingroup sm8250_groups[] = { [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), [180] = UFS_RESET(ufs_reset, 0xb8000), - [181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6), + [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6), [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), }; @@ -1320,7 +1320,7 @@ static const struct msm_pinctrl_soc_data sm8250_pinctrl = { .nfunctions = ARRAY_SIZE(sm8250_functions), .groups = sm8250_groups, .ngroups = ARRAY_SIZE(sm8250_groups), - .ngpios = 181, + .ngpios = 180, .tiles = sm8250_tiles, .ntiles = ARRAY_SIZE(sm8250_tiles), };
Correct sdc2_clk pin definition (register offset) and ngpios (SM8250 has 180 GPIO pins). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 4e3ec9e407ad5058003309072b37111f7b8c900a --- drivers/pinctrl/qcom/pinctrl-sm8250.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)