From patchwork Mon May 7 02:25:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 909504 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=alliedtelesis.co.nz Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.b="OHpgo9Qp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40fRLj4Tnkz9ryk for ; Mon, 7 May 2018 12:26:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751878AbeEGC0E (ORCPT ); Sun, 6 May 2018 22:26:04 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:50809 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751831AbeEGC0D (ORCPT ); Sun, 6 May 2018 22:26:03 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 8548D806B7; Mon, 7 May 2018 14:26:01 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1525659961; bh=uoahMCEtzn4YXNgJ/3HQEzuoq8MrPxvLK9KGkRLtgSI=; h=From:To:Cc:Subject:Date; b=OHpgo9Qp3QslbIWS0MY84b4vlf3hUDP7Oapky0cn8C+4Z5xy0IGH7IF7xogi+ewYB AFcJM7f/2lKPsdRhIRZNtppwA0xSr4DJVSLliSAbWFdL6N6b21SbYu6BMugP875m3O RK/+wTlv96bfAuNbkmxdRWsXx8TU1oevHN5uXzjA= Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 07 May 2018 14:26:01 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 6414313ED56; Mon, 7 May 2018 14:26:02 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 50F2B1E019A; Mon, 7 May 2018 14:26:01 +1200 (NZST) From: Chris Packham To: gregory.clement@bootlin.com, linus.walleij@linaro.org, linux-gpio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Chris Packham , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , linux-arm-kernel@lists.infradead.org Subject: [PATCH] pinctrl: mvebu: use correct MPP sel value for dev pins Date: Mon, 7 May 2018 14:25:55 +1200 Message-Id: <20180507022555.31645-1-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.17.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The "dev" function is selected with the value 0x4 not 0x01. Fixes: commit d7ae8f8dee7f ("pinctrl: mvebu: pinctrl driver for 98DX3236 SoC") Signed-off-by: Chris Packham --- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 28b199796fae..5e828468e43d 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -437,34 +437,34 @@ static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = { MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)), MPP_MODE(21, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad0", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "ad0", V_98DX3236_PLUS)), MPP_MODE(22, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad1", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "ad1", V_98DX3236_PLUS)), MPP_MODE(23, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad2", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "ad2", V_98DX3236_PLUS)), MPP_MODE(24, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad3", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "ad3", V_98DX3236_PLUS)), MPP_MODE(25, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad4", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "ad4", V_98DX3236_PLUS)), MPP_MODE(26, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad5", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "ad5", V_98DX3236_PLUS)), MPP_MODE(27, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad6", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "ad6", V_98DX3236_PLUS)), MPP_MODE(28, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "ad7", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "ad7", V_98DX3236_PLUS)), MPP_MODE(29, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "a0", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "a0", V_98DX3236_PLUS)), MPP_MODE(30, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), - MPP_VAR_FUNCTION(0x1, "dev", "a1", V_98DX3236_PLUS)), + MPP_VAR_FUNCTION(0x4, "dev", "a1", V_98DX3236_PLUS)), MPP_MODE(31, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS),