From patchwork Mon Feb 15 12:17:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 582867 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3A8221402DD for ; Mon, 15 Feb 2016 23:14:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=sXwQPZQS; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753118AbcBOMOf (ORCPT ); Mon, 15 Feb 2016 07:14:35 -0500 Received: from mail-pf0-f173.google.com ([209.85.192.173]:35313 "EHLO mail-pf0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753110AbcBOMOd (ORCPT ); Mon, 15 Feb 2016 07:14:33 -0500 Received: by mail-pf0-f173.google.com with SMTP id c10so88493157pfc.2; Mon, 15 Feb 2016 04:14:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:subject; bh=qW6vBcICYVpuHrNwoZU0yhZQ2CRl2y1xjPbGC8Ckvew=; b=sXwQPZQS4bD5EhIQMaEigaF5/N4Y/6iR0OO+RWS5itwM8fBnnw9OySC4xAMtt7Zoqe xJ/Ew2aztnDn9S852p5fRf9mBuLkpg75/jE+Lp2ygvs+gXuhFyvMAr6OY1UaykWm9IFk 9wfplAVIIRFZuKXzLy83b69ofaywL2DB6l/T8hdJC6BPjc6L/+XnMlhj6Hhiyl3qj36G qmMUFBvs+ruI+yGCCOeU98O8tUygydUDzrO4NagpMrrU6MBM57BIvwGSOB8Cew9wadQ/ 7YOy37JhUsEZm/14NtlBqFgBuKrYxKHXFbVx/lZv+zU+hKVS3ugHIK8Cnv2ZIcFUSCHr 7rpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:date:message-id:subject; bh=qW6vBcICYVpuHrNwoZU0yhZQ2CRl2y1xjPbGC8Ckvew=; b=dC+utOhmf7zHkeIxHnM5WtcviamOr1BFrw0MQ9aHLL5SHgc3SGRXRF2owd33CnC3k2 xKNLMEyeFuTkwuFf3bb4ELWvAhESKf0vmxq8bIEvvTOg5KnzoEUBoapEFGWuusC2bg1U pfQJC1IDScnIybCN90qnUy6tmtHGa5NAU2w4baA/Y2KX47jKQxZA4bq+BpyKE7IZGK01 +B7N29UnCFLUSXFMBZ65/Ig47kkFPOpcUw+eAfsvTmLQ0Gim+mI1RcHqLL52RkbwsxO5 kq1TpXnAajNosg8RIL6o0tGdeq1cJOcsJeXdHfvY0uA2WkC8mo20+DtaSjF/8XAk8pyI QcLw== X-Gm-Message-State: AG10YOSJhWSzQlXwenyQgpw7dSpcwBmF8zybY7MOc0YrOCeE17hWvGY58cs4S4qIE7Xg8g== X-Received: by 10.98.75.10 with SMTP id y10mr22929799pfa.32.1455538472644; Mon, 15 Feb 2016 04:14:32 -0800 (PST) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by smtp.gmail.com with ESMTPSA id s197sm38235222pfs.62.2016.02.15.04.14.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 15 Feb 2016 04:14:31 -0800 (PST) From: Magnus Damm To: linux-renesas-soc@vger.kernel.org Cc: linus.walleij@linaro.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, horms@verge.net.au, geert@glider.be, laurent.pinchart@ideasonboard.com, Magnus Damm Date: Mon, 15 Feb 2016 21:17:19 +0900 Message-Id: <20160215121719.27056.43809.sendpatchset@little-apple> Subject: [PATCH] pinctrl: sh-pfc: r8a7795: Add support for INTC-EX IRQ pins Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: Magnus Damm Most pins on the r8a7795 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". Tested on r8a7795 Salvator-X with an external loop back adapter on EXIO_D that connects pin 9 (IRQ2/GP2_02) and pin 26 (ExA22/GP2_06). Signed-off-by: Magnus Damm Reviewed-by: Geert Uytterhoeven --- Developed on top of renesas-drivers-2016-02-09-v4.5-rc3 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 60 ++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html --- 0001/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ work/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 2016-02-15 21:05:24.500513000 +0900 @@ -1835,6 +1835,50 @@ static const unsigned int i2c6_c_mux[] = SDA6_C_MARK, SCL6_C_MARK, }; +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3173,6 +3217,12 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), SH_PFC_PIN_GROUP(msiof0_ss1), @@ -3439,6 +3489,15 @@ static const char * const i2c6_groups[] "i2c6_c", }; +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -3686,6 +3745,7 @@ static const struct sh_pfc_function pinm SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c6), + SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2),