From patchwork Thu May 3 08:04:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 907881 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40c7Dl2Vk0z9s3Z for ; Thu, 3 May 2018 18:12:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751069AbeECIMx (ORCPT ); Thu, 3 May 2018 04:12:53 -0400 Received: from lucky1.263xmail.com ([211.157.147.131]:37044 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750945AbeECIMs (ORCPT ); Thu, 3 May 2018 04:12:48 -0400 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.224]) by lucky1.263xmail.com (Postfix) with ESMTP id 74C4896AF9; Thu, 3 May 2018 16:12:41 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id C9FD43C7; Thu, 3 May 2018 16:12:41 +0800 (CST) X-IP-DOMAINF: 1 X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: linus.walleij@linaro.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <39b847520d44308a2610773d9479004d> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 27370UCJ1J7; Thu, 03 May 2018 16:12:42 +0800 (CST) From: Shawn Lin To: Linus Walleij Cc: Heiko Stuebner , linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, Shawn Lin Subject: [PATCH] pinctrl: rockchip: Add set_config callback support for gpiolib Date: Thu, 3 May 2018 16:04:42 +0800 Message-Id: <1525334682-222918-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Could only support PIN_CONFIG_INPUT_DEBOUNCE now as the HW block is too simple to support others. But even wrt. debounce capability, it now could only support very limited period of time to satisfy the real usecase. But still be useful to enable the crippled HW debounce to prevent any spurious glitches from waking up the system if the gpio is conguired as wakeup interrupt source. Signed-off-by: Shawn Lin Reviewed-by: Heiko Stuebner --- Hi Linus, This patch comes from our early discussion of debounce of cd-gpios for sd card that I pointed out that rockchip's platform lacks HW debounce support, but I think it's overkilled. It does have HW debounce but not really useful as the debounce period is toooo short and almost fixed. But something is better than nothing, so I'd like to enable it for filtering glitches, since cd-gpios for sd card is allow to configured as wakeup source. ;) drivers/pinctrl/pinctrl-rockchip.c | 52 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 3924779..14e80de 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2555,6 +2555,57 @@ static int rockchip_gpio_direction_output(struct gpio_chip *gc, return pinctrl_gpio_direction_output(gc->base + offset); } +static void rockchip_gpio_set_debounce(struct gpio_chip *gc, + unsigned int offset, bool enable) +{ + struct rockchip_pin_bank *bank = gpiochip_get_data(gc); + void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; + unsigned long flags; + u32 data; + + clk_enable(bank->clk); + raw_spin_lock_irqsave(&bank->slock, flags); + + data = readl(reg); + if (enable) + data |= BIT(offset); + else + data &= ~BIT(offset); + writel(data, reg); + + raw_spin_unlock_irqrestore(&bank->slock, flags); + clk_disable(bank->clk); +} + +/* + * gpiolib set_config callback function. The setting of the pin + * mux function as 'gpio output' will be handled by the pinctrl subsystem + * interface. + */ +static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, + unsigned long config) +{ + enum pin_config_param param = pinconf_to_config_param(config); + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + rockchip_gpio_set_debounce(gc, offset, true); + /* + * Rockchip's gpio could only support up to one period + * of the debounce clock(pclk), which is far away from + * satisftying the requirement, as pclk is usually near + * 100MHz shared by all peripherals. So the fact is it + * has crippled debounce capability could only be useful + * to prevent any spurious glitches from waking up the system + * if the gpio is conguired as wakeup interrupt source. Let's + * still return -ENOTSUPP as before, to make sure the caller + * of gpiod_set_debounce won't change its behaviour. + */ + default: + return -ENOTSUPP; + } +} + /* * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin * and a virtual IRQ, if not already present. @@ -2580,6 +2631,7 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) .get_direction = rockchip_gpio_get_direction, .direction_input = rockchip_gpio_direction_input, .direction_output = rockchip_gpio_direction_output, + .set_config = rockchip_gpio_set_config, .to_irq = rockchip_gpio_to_irq, .owner = THIS_MODULE, };