From patchwork Fri Oct 28 11:24:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 688357 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3t51yh2PDlz9sdn for ; Fri, 28 Oct 2016 22:40:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753167AbcJ1LkL (ORCPT ); Fri, 28 Oct 2016 07:40:11 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:14252 "EHLO hkmmgate102.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752497AbcJ1LkK (ORCPT ); Fri, 28 Oct 2016 07:40:10 -0400 Received: from hkpgpgate101.nvidia.com (Not Verified[10.18.92.9]) by hkmmgate102.nvidia.com id ; Fri, 28 Oct 2016 19:37:10 +0800 Received: from HKMAIL103.nvidia.com ([10.18.67.137]) by hkpgpgate101.nvidia.com (PGP Universal service); Fri, 28 Oct 2016 04:40:06 -0700 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Fri, 28 Oct 2016 04:40:06 -0700 Received: from DRBGMAIL103.nvidia.com (10.18.16.22) by HKMAIL103.nvidia.com (10.18.16.12) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 28 Oct 2016 11:40:00 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by DRBGMAIL103.nvidia.com (10.18.16.22) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Fri, 28 Oct 2016 11:39:59 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1210.3 via Frontend Transport; Fri, 28 Oct 2016 11:39:57 +0000 From: Laxman Dewangan To: CC: , , "Laxman Dewangan" Subject: [PATCH] pinctrl: generic: Parse pinmux init nodes if node status is okay Date: Fri, 28 Oct 2016 16:54:21 +0530 Message-ID: <1477653861-11921-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org During pinmux registration, pinmux table is parsed from DT for making the pinmux table configuration of pins. Parse the only those node whose status is not disabled. This will help on reusing the pin configuration table across platform and disabling the node by status property if that node is not needed on given platform. Signed-off-by: Laxman Dewangan --- drivers/pinctrl/pinconf-generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 5020ae5..ce3335a 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -381,7 +381,7 @@ int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev, if (ret < 0) goto exit; - for_each_child_of_node(np_config, np) { + for_each_available_child_of_node(np_config, np) { ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, &reserved_maps, num_maps, type); if (ret < 0)