From patchwork Fri Jun 17 12:03:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 636973 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rWJpZ3rTjz9t1r for ; Fri, 17 Jun 2016 22:04:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161113AbcFQMEu (ORCPT ); Fri, 17 Jun 2016 08:04:50 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15816 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161080AbcFQMEs (ORCPT ); Fri, 17 Jun 2016 08:04:48 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 17 Jun 2016 05:04:28 -0700 Received: from HQMAIL101.nvidia.com ([172.20.187.10]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 17 Jun 2016 05:01:09 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 17 Jun 2016 05:01:09 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 17 Jun 2016 12:04:47 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 17 Jun 2016 12:04:47 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.108]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Fri, 17 Jun 2016 05:04:47 -0700 From: Jon Hunter To: Thierry Reding , David Airlie , Stephen Warren , Alexandre Courbot , Wolfram Sang , Linus Walleij , Rob Herring , Mark Rutland CC: , , , , , Jon Hunter Subject: [RFC PATCH 12/13] arm64: tegra: Add sor-safe clock to DPAUX binding Date: Fri, 17 Jun 2016 13:03:46 +0100 Message-ID: <1466165027-17917-13-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466165027-17917-1-git-send-email-jonathanh@nvidia.com> References: <1466165027-17917-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Populate the 'sor-safe' clock for DPAUX devices on Tegra210 that require this clock for operation. Update the compatability string for the DPAUX instance at address 0x545c0000 to be "nvidia,tegra210-dpaux" to ensure that the 'sor-safe' clock is enabled for this device. Signed-off-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 94f780b43037..78bcc87b627d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -30,8 +30,9 @@ reg = <0x0 0x54040000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; + <&tegra_car TEGRA210_CLK_PLL_DP>, + <&tegra_car TEGRA210_CLK_SOR_SAFE>; + clock-names = "dpaux", "parent", "sor-safe"; resets = <&tegra_car 207>; reset-names = "dpaux"; power-domains = <&pd_sor>; @@ -175,12 +176,13 @@ }; dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra124-dpaux"; + compatible = "nvidia,tegra210-dpaux"; reg = <0x0 0x545c0000 0x0 0x00040000>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_DPAUX>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; + <&tegra_car TEGRA210_CLK_PLL_DP>, + <&tegra_car TEGRA210_CLK_SOR_SAFE>; + clock-names = "dpaux", "parent", "sor-safe"; resets = <&tegra_car 181>; reset-names = "dpaux"; power-domains = <&pd_sor>;