From patchwork Wed May 11 07:34:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 620916 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3r4SZV6gNsz9t3n for ; Wed, 11 May 2016 17:35:14 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b=mJMlfno+; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751537AbcEKHe4 (ORCPT ); Wed, 11 May 2016 03:34:56 -0400 Received: from mail-wm0-f43.google.com ([74.125.82.43]:36302 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751360AbcEKHek (ORCPT ); Wed, 11 May 2016 03:34:40 -0400 Received: by mail-wm0-f43.google.com with SMTP id n129so207206292wmn.1 for ; Wed, 11 May 2016 00:34:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cbVQxJocwo53rh6AvH4m6U4yfpWEnDQjOqKHss5ib2w=; b=mJMlfno+655QXvWnat/+RDVx+7q/jlpuENpkI6dH/05SaS/4hKu7ZdotJKG1HGtlY7 i1g6i7KmSsxI00NjJSAQpy31KikMkBLS57L5JWDE5+Q/Eazda6KAOHWLRVAPpY8F3ReC SZCgLq9qFuiwEjZMczxlI2AXf8bWd1QA5rQTY4WL0mrW8LobJjGTFy3gA/Fp3AZafxys 1jgWgzg4t+05EZHcxsfxBmN1WfpaHOwMgaaxjEGPZoR9kHxsKwg8I4o/4U2M/V40sXTv MiQ26Dp4zuiAIdghfAbKk6Cypws0bgO5yrwzSW1Y+GT/9Tm2KZ5UGEJyXYfoSd0CHgkB ZLHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cbVQxJocwo53rh6AvH4m6U4yfpWEnDQjOqKHss5ib2w=; b=DFKtc8edpc98Y8bsbvHJC26R4rZOp8EGzB5zzHtA+mAzpE6U4IGj6aGAr2je6vrfcd g7/sYX3ljC5b8veKIavqvGlmgoI2kIb9mXex8J6wP5FSXAs1nz/Rizfc0XKeOtI3yKaN a1rsgZ65OhIPrRe6Y8rEO662/LdHmcwPW1hZShxLjsT59oZdhooRjRdz47bvi838DY2R kdc0raZmemENWpOP6zhswumWuUhiTQqxlfZ1JNaF+q8FwkUinomXppenJz32N2mgnAtn KBIrVGu1PR75y2xCNneHK2dXfX/79zp2GKgC/c71DZjtXHT6uViQHMYDKnLz8+GiHo3r kcgg== X-Gm-Message-State: AOPr4FXaJYqh3u/cL3UKlvOXLwR03ckOZElUUbryT3el3o9eL8xehyjiodiG4WP2+/GI/B9+ X-Received: by 10.28.161.131 with SMTP id k125mr2531307wme.53.1462952079173; Wed, 11 May 2016 00:34:39 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id m14sm6971477wmc.4.2016.05.11.00.34.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 May 2016 00:34:38 -0700 (PDT) From: Neil Armstrong To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Neil Armstrong Subject: [PATCH v2 2/2] dt-bindings: Add Oxford Semiconductor OXNAS pinctrl and gpio bindings Date: Wed, 11 May 2016 09:34:22 +0200 Message-Id: <1462952062-5316-3-git-send-email-narmstrong@baylibre.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1462952062-5316-1-git-send-email-narmstrong@baylibre.com> References: <1462952062-5316-1-git-send-email-narmstrong@baylibre.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add pinctrl and gpio DT bindings for Oxford Semiconductor OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by: Neil Armstrong Acked-by: Rob Herring --- .../devicetree/bindings/gpio/gpio_oxnas.txt | 47 ++++++++++++++++++ .../devicetree/bindings/pinctrl/oxnas,pinctrl.txt | 57 ++++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio_oxnas.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt new file mode 100644 index 0000000..928ed4f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio_oxnas.txt @@ -0,0 +1,47 @@ +* Oxford Semiconductor OXNAS SoC GPIO Controller + +Please refer to gpio.txt for generic information regarding GPIO bindings. + +Required properties: + - compatible: "oxsemi,ox810se-gpio" + - reg: Base address and length for the device. + - interrupts: The port interrupt shared by all pins. + - gpio-controller: Marks the port as GPIO controller. + - #gpio-cells: Two. The first cell is the pin number and + the second cell is used to specify the gpio polarity as defined in + defined in : + 0 = GPIO_ACTIVE_HIGH + 1 = GPIO_ACTIVE_LOW + - interrupt-controller: Marks the device node as an interrupt controller. + - #interrupt-cells: Two. The first cell is the GPIO number and second cell + is used to specify the trigger type as defined in + : + IRQ_TYPE_EDGE_RISING + IRQ_TYPE_EDGE_FALLING + IRQ_TYPE_EDGE_BOTH + - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the + gpio base and count, should be in the format of numeric-gpio-range as + specified in the gpio.txt file. + +Example: + +gpio0: gpio@0 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; +}; + +keys { + ... + + button-esc { + label = "ESC"; + linux,code = <1>; + gpios = <&gpio0 12 0>; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt new file mode 100644 index 0000000..d607432 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt @@ -0,0 +1,57 @@ +* Oxford Semiconductor OXNAS SoC Family Pin Controller + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +OXNAS 'pin configuration node' is a node of a group of pins which can be +used for a specific device or function. This node represents configurations of +pins, optional function, and optional mux related configuration. + +Required properties for pin controller node: + - compatible: "oxsemi,ox810se-pinctrl" + - oxsemi,sys-ctrl: a phandle to the system controller syscon node + +Required properties for pin configuration sub-nodes: + - pins: List of pins to which the configuration applies. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. + - bias-pull-up: Enable weak pull-up. + +Example: + +pinctrl: pinctrl { + compatible = "oxsemi,ox810se-pinctrl"; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + pinctrl_uart2: pinctrl_uart2 { + uart2a { + pins = "gpio31"; + function = "fct3"; + }; + uart2b { + pins = "gpio32"; + function = "fct3"; + }; + }; +}; + +uart2: serial@900000 { + compatible = "ns16550a"; + reg = <0x900000 0x100000>; + clocks = <&sysclk>; + interrupts = <29>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +};