From patchwork Mon May 2 17:23:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 617630 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qzBKS4qgWz9t3x for ; Tue, 3 May 2016 03:35:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754665AbcEBRfj (ORCPT ); Mon, 2 May 2016 13:35:39 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:18288 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754224AbcEBRfi (ORCPT ); Mon, 2 May 2016 13:35:38 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 02 May 2016 10:35:41 -0700 Received: from HQHUB101.nvidia.com ([172.20.187.24]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 02 May 2016 10:34:40 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 02 May 2016 10:34:40 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQHUB101.nvidia.com (172.20.187.24) with Microsoft SMTP Server (TLS) id 8.3.406.0; Mon, 2 May 2016 10:35:37 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Mon, 2 May 2016 17:35:36 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Mon, 2 May 2016 17:35:34 +0000 From: Laxman Dewangan To: , , CC: , , , , , Laxman Dewangan Subject: [PATCH V2] pinctrl: tegra: Correctly check the supported configuration Date: Mon, 2 May 2016 22:53:24 +0530 Message-ID: <1462209804-16582-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The pincontrol registers of Tegra chips has multiple filed per registers. There is two type of registers mux and drive. All configurations belongs to one of these registers. If any configurations are supported then _bit is set to bit position of these registers otherwise -1 to not support it. The member is defined as s32 _bit:6; So if config is not supported ifor given SoC then it is set to -1 in soc pinmmux table. In common driver code, to find out that given config is supported or not, it is checked as: s8 bit = _bit; if (bit > 31) { /* Not supported config */ } But in this case, bit is s8 and hence for non supporting it is -1. Correct the check as: if (bit < 0) { /* Not supported config */ } Fixes: e4c02dced975cb ("pinctrl: tegra: use signed bitfields for optional fields") Signed-off-by: Laxman Dewangan Signed-off-by: lines. I assume this can be fixed when the patch is applied. Acked-by: Stephen Warren --- drivers/pinctrl/tegra/pinctrl-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 861baf2..6e82b29 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -417,7 +417,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, return -ENOTSUPP; } - if (*reg < 0 || *bit > 31) { + if (*reg < 0 || *bit < 0) { if (report_err) { const char *prop = "unknown"; int i;