From patchwork Thu Mar 31 15:09:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 604185 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qbSdx2Zmbz9s4n for ; Fri, 1 Apr 2016 02:11:33 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=lYpvIGqy; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756677AbcCaPLJ (ORCPT ); Thu, 31 Mar 2016 11:11:09 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:34628 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757421AbcCaPJ6 (ORCPT ); Thu, 31 Mar 2016 11:09:58 -0400 Received: by mail-wm0-f65.google.com with SMTP id p65so24481604wmp.1; Thu, 31 Mar 2016 08:09:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Fplu2Mlpq3cAB5ySRNPfu/1FL+bkQC9YOaGWA/kxWF0=; b=lYpvIGqy4pYwm/NPD0ELuIX7o6H6IPxnaivleKNV1twofjvJcFhVnIQOu49sFymwmE 9gbPh8cr5VRC/C7SZ53sWjzxM9fBGDPpD9kI4TE0akw7wlKRfQWUjoSj3AtjOYee+E+F w4uLfgGanxteY5MfqTNCmgtqHV70pMMRmQYcLMDtfJpFAdZ+Dv8c9SB10QsHW+yUoySN ORfmVldyG10wgXdi8x7E/llSJo1KRNi0ppRCszp991OmYlwSajwOvpn2C03MC7FJl7/b 1OzbNg+FqVxzJNO+4+WSY3fWHBijmA4ZsWGOpFO/AZQkjvp82FrE9QtuyVjOkSa3O52w 0P/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Fplu2Mlpq3cAB5ySRNPfu/1FL+bkQC9YOaGWA/kxWF0=; b=hAhxmlKl3aQzMhNcl4RvsgqP0rQ0b13JLvNBbPqAwDYoTZnvavXp5afugxybOnTi+d owSl9mB3RtAWhXAAlrcJDbstJcTTCJaWq0gXGwAqxch2GN/xq5KjllQofsOGK+nqPU/e ieKxaEVMp+YM6wWpVkn963ddmoRpSPKXBjuO96JBb/58r851r1vP3xnNtsiCeh69mHcB MOwbPUoMnrUw0AIIKas+HpjfN8si2hfbNWnwUl1cThA4tPL5O+fTKozq9JXK5ov2Oy1x mdvb+K4e6lN94bzGX0zLBza9XndxZVR4vjI+QP5e6LWC7qBWdrMeCgbcbbmzlOjO/IQc O6BA== X-Gm-Message-State: AD7BkJKW+KP4oKSadhTtmFYDkE/BPSQKA23LaFZCnTqCFnovMY6QJCbbfKzaHB9dFgsezA== X-Received: by 10.28.126.210 with SMTP id z201mr3455617wmc.102.1459436991583; Thu, 31 Mar 2016 08:09:51 -0700 (PDT) Received: from lmecul0520.st.com. (241.204.154.77.rev.sfr.net. [77.154.204.241]) by smtp.gmail.com with ESMTPSA id i5sm9505781wjx.15.2016.03.31.08.09.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 31 Mar 2016 08:09:50 -0700 (PDT) From: Maxime Coquelin To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Linus Walleij , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Daniel Thompson , bruherrera@gmail.com, lee.jones@linaro.org Subject: [PATCH v2 5/9] Documentation: dt-bindings: Add IRQ related properties of STM32 pinctrl Date: Thu, 31 Mar 2016 17:09:35 +0200 Message-Id: <1459436979-17275-6-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1459436979-17275-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1459436979-17275-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Signed-off-by: Maxime Coquelin Acked-by: Rob Herring --- Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt index 7b4800cc251e..dd95becba966 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt @@ -13,6 +13,9 @@ Required properies: - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to gpio-bank node (children). + - interrupt-parent: phandle of the interrupt parent to which the external + GPIO interrupts are forwarded to. + - st,syscfg: phandle of the syscfg node used for IRQ mux selection. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins.