From patchwork Fri Dec 11 08:25:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 555594 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5EDE61402D9 for ; Fri, 11 Dec 2015 19:26:48 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Ci8YKJRh; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754204AbbLKIZb (ORCPT ); Fri, 11 Dec 2015 03:25:31 -0500 Received: from mail-wm0-f53.google.com ([74.125.82.53]:38515 "EHLO mail-wm0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753972AbbLKIZX (ORCPT ); Fri, 11 Dec 2015 03:25:23 -0500 Received: by wmec201 with SMTP id c201so59176787wme.1; Fri, 11 Dec 2015 00:25:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2B2l1hNwr5UJ8YR/Bs6iAh3V0L5Pz28Y4fX1d3ffZD4=; b=Ci8YKJRh27OWLZ3g+0nb3uw3mDrntTZRwIdRmbgltCCYvkXXVAgUTLZy2OcjnkW9/V H7/ON189n8aQCWHELUkr/I5pnFlye81A5h64MMA5J9yKJooJS1jKPqhyqIQfTGS9A4nC ZMGU45WskroIBMp7AGwqFV+EVVy3myzGVJeA6Ru2LPOvdvPJbmgPOJyWOY4DPdXg++DM 5JUGAOII5Io/WSb1Xg1ujLOCAQLiA2QQd+RsL5jXeIq0N0YQNbH+Ka6oOANjCNr8rtg3 vkDs9HAvchQJLHnfTIOvCNPviTRYxHfD64fWQltbeDSQc8g2HOjK29cTjJUDRpNbXivV JtsA== X-Received: by 10.28.97.197 with SMTP id v188mr4288405wmb.63.1449822321678; Fri, 11 Dec 2015 00:25:21 -0800 (PST) Received: from lmecul0520.st.com. (241.202.154.77.rev.sfr.net. [77.154.202.241]) by smtp.gmail.com with ESMTPSA id w67sm2308517wmw.17.2015.12.11.00.25.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 Dec 2015 00:25:21 -0800 (PST) From: Maxime Coquelin To: patrice.chotard@st.com, Linus Walleij , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, afaerber@suse.de, devicetree@vger.kernel.org, Daniel Thompson , bruherrera@gmail.com Subject: [PATCH v3 7/9] ARM: dts: Add USART1 pin config to STM32F429 boards Date: Fri, 11 Dec 2015 09:25:04 +0100 Message-Id: <1449822306-9035-8-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449822306-9035-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1449822306-9035-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch selects USART1 pin configuration on PA9/PA10 pins for both Eval and Disco boards. Acked-by: Linus Walleij Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stm32429i-eval.dts | 2 ++ arch/arm/boot/dts/stm32f429-disco.dts | 2 ++ arch/arm/boot/dts/stm32f429.dtsi | 13 +++++++++++++ 3 files changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 6964fc9..71fe17a 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index f0b731d..e3ce796 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 62d2b3d..1cf713e 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -263,6 +263,19 @@ clocks = <&rcc 0 266>; st,bank-name = "GPIOK"; }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + bias-disable; + }; + }; }; rcc: rcc@40023810 {