From patchwork Fri Dec 11 08:25:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 555593 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C7CDF1402D9 for ; Fri, 11 Dec 2015 19:26:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=omLaqbw0; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754080AbbLKIZc (ORCPT ); Fri, 11 Dec 2015 03:25:32 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:34699 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753342AbbLKIZW (ORCPT ); Fri, 11 Dec 2015 03:25:22 -0500 Received: by wmdc17 with SMTP id c17so3652446wmd.1; Fri, 11 Dec 2015 00:25:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2ik1rWQ36J0TORf2xcmEiWda7j2Bltz8vheqFV7Y6Ss=; b=omLaqbw0C0CBAH8gotDuwhW/WO+4pmkQk0l2N+v25rH8C4sx4NvHOGM0n0oCQv/ooy 5ZNbWbKwRBnDbyGb2tpKcHzkOOApej9xm8W3HkiMnTfl3t26ZFWRFHyHWgrVPnxBHvz/ 0h4PcoIdCmfPDjfQuTi5kTMl9880bBGfZn4keR5dc1QDoeZMC4/bOy5y5ridpOA0l3y9 f7RIE0GuI70rxUz9KkzXQfMvJs7/OOb6QCqruShrFR+26nFR0ovaiTfnehbiA97lh98q APufApCUm0mCDLjWRMaAbDHpqjWHN+g3+e++/qAW3f9gugp1SRw/m5jA4U2BadoGUKcP CXyg== X-Received: by 10.194.178.70 with SMTP id cw6mr17920413wjc.73.1449822320208; Fri, 11 Dec 2015 00:25:20 -0800 (PST) Received: from lmecul0520.st.com. (241.202.154.77.rev.sfr.net. [77.154.202.241]) by smtp.gmail.com with ESMTPSA id w67sm2308517wmw.17.2015.12.11.00.25.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 11 Dec 2015 00:25:19 -0800 (PST) From: Maxime Coquelin To: patrice.chotard@st.com, Linus Walleij , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, afaerber@suse.de, devicetree@vger.kernel.org, Daniel Thompson , bruherrera@gmail.com Subject: [PATCH v3 6/9] ARM: dts: Add pinctrl node to STM32F429 Date: Fri, 11 Dec 2015 09:25:03 +0100 Message-Id: <1449822306-9035-7-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449822306-9035-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1449822306-9035-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The STM32F429 MCU has 11 GPIO banks, with 16 pins per bank. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stm32f429.dtsi | 97 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 5e1e234..62d2b3d 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -46,6 +46,7 @@ */ #include "armv7-m.dtsi" +#include / { clocks { @@ -168,6 +169,102 @@ status = "disabled"; }; + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + clocks = <&rcc 0 256>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + clocks = <&rcc 0 257>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + clocks = <&rcc 0 258>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + clocks = <&rcc 0 259>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&rcc 0 260>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + clocks = <&rcc 0 261>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + clocks = <&rcc 0 262>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + clocks = <&rcc 0 263>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&rcc 0 264>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + clocks = <&rcc 0 265>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + clocks = <&rcc 0 266>; + st,bank-name = "GPIOK"; + }; + }; + rcc: rcc@40023810 { #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";