From patchwork Tue Dec 8 12:45:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 553887 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48FFB14032F for ; Tue, 8 Dec 2015 23:46:37 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=VFD5aOMY; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932976AbbLHMpb (ORCPT ); Tue, 8 Dec 2015 07:45:31 -0500 Received: from mail-wm0-f48.google.com ([74.125.82.48]:33377 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932936AbbLHMp1 (ORCPT ); Tue, 8 Dec 2015 07:45:27 -0500 Received: by wmec201 with SMTP id c201so210721198wme.0; Tue, 08 Dec 2015 04:45:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2B2l1hNwr5UJ8YR/Bs6iAh3V0L5Pz28Y4fX1d3ffZD4=; b=VFD5aOMYOwZVZtxkyn4L0kdpgFxj2yujNZnwUOeOc0MaJazqx3pLefW+YWOJajuFPr A40ycFnzTAeaKvsIUi+6SRKn29jYFtM6ftdpvdu2Nh7V/P475jEHNdjrf39RTJgrERqD 3/gZsj7y2Cx/4hqkI1b/A0ZUbLGeHHJ5JHL6OQevmQjItTm5AM4YQzwm1vFpQX/dokUH hZv1/p220Kr6WtxcyrM7/mUcLKTwJxXB3/+AP0+Ko4K6AnmLpzFxXWMZemuqMSnVODxV WqAiR9uogNT9n4YzXenWpZqqY9jIw0GkG/xbm2Lc5KbWjooqZT1eDq4fNDWeqk1laWuh B43g== X-Received: by 10.194.19.100 with SMTP id d4mr3677308wje.18.1449578726368; Tue, 08 Dec 2015 04:45:26 -0800 (PST) Received: from lmecul0520.st.com. (111.202.154.77.rev.sfr.net. [77.154.202.111]) by smtp.gmail.com with ESMTPSA id d2sm2871311wjy.16.2015.12.08.04.45.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Dec 2015 04:45:25 -0800 (PST) From: Maxime Coquelin To: Linus Walleij , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, arnd@arndb.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, afaerber@suse.de, devicetree@vger.kernel.org, Daniel Thompson , bruherrera@gmail.com Subject: [PATCH v3 7/9] ARM: dts: Add USART1 pin config to STM32F429 boards Date: Tue, 8 Dec 2015 13:45:09 +0100 Message-Id: <1449578711-6141-8-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449578711-6141-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1449578711-6141-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch selects USART1 pin configuration on PA9/PA10 pins for both Eval and Disco boards. Acked-by: Linus Walleij Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stm32429i-eval.dts | 2 ++ arch/arm/boot/dts/stm32f429-disco.dts | 2 ++ arch/arm/boot/dts/stm32f429.dtsi | 13 +++++++++++++ 3 files changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 6964fc9..71fe17a 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index f0b731d..e3ce796 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 62d2b3d..1cf713e 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -263,6 +263,19 @@ clocks = <&rcc 0 266>; st,bank-name = "GPIOK"; }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + bias-disable; + }; + }; }; rcc: rcc@40023810 {