| Message ID | 1445557577-27383-3-git-send-email-vishnupatekar0510@gmail.com |
|---|---|
| State | New |
| Headers | show |
Hi, On Fri, Oct 23, 2015 at 07:46:16AM +0800, Vishnu Patekar wrote: > + memory { > + reg = <0x40000000 0x80000000>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; Shouldn't the number of CPUs be 8? > + clock-frequency = <24000000>; > + arm,cpu-registers-not-fw-configured; > + }; Is there some u-boot support for this SoC yet? If so, both the memory node and the clock-frequency and arm,cpu-registers-not-fw-configured properties are useless (and harmful for the latter). > + soc@01c00000 { Please remove the address. It's both wrong and useless. > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + gic: interrupt-controller@01c81000 { > + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + pio: pinctrl@01c20800 { > + compatible = "allwinner,sun8i-a83t-pinctrl"; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; Please align these lines with the first one, like you did for the GIC's reg for example. > + reg = <0x01c20800 0x400>; > + clocks = <&osc24M>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <3>; > + #gpio-cells = <3>; > + > + i2c0_pins_a: i2c0@0 { > + allwinner,pins = "PH0", "PH1"; > + allwinner,function = "i2c0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + i2c1_pins_a: i2c1@0 { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + i2c2_pins_a: i2c2@0 { > + allwinner,pins = "PH4", "PH5"; > + allwinner,function = "i2c2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + mmc0_pins_a: mmc0@0 { > + allwinner,pins = "PF0", "PF1", "PF2", > + "PF3", "PF4", "PF5"; > + allwinner,function = "mmc0"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + mmc1_pins_a: mmc1@0 { > + allwinner,pins = "PG0", "PG1", "PG2", > + "PG3", "PG4", "PG5"; > + allwinner,function = "mmc1"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + mmc2_8bit_pins: mmc2_8bit { > + allwinner,pins = "PC5", "PC6", "PC8", > + "PC9", "PC10", "PC11", > + "PC12", "PC13", "PC14", > + "PC15"; > + allwinner,function = "mmc2"; > + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + uart0_pins_a: uart0@0 { > + allwinner,pins = "PF2", "PF4"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + > + uart0_pins_b: uart0@1 { > + allwinner,pins = "PB9", "PB10"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; Are you going to use all these options? Thanks! Maxime
On Fri, Oct 23, 2015 at 7:46 AM, Vishnu Patekar <vishnupatekar0510@gmail.com> wrote: > Allwinner A83T is new octa-core cortex-a7 SOC. > This adds the basic dtsi, the clocks differs from > earlier sun8i SOCs. > > Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 247 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 247 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > new file mode 100644 > index 0000000..e85995f > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > @@ -0,0 +1,247 @@ > + cpu@100 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <4>; > + }; > + > + cpu@101 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <5>; > + }; > + cpu@102 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <6>; > + }; > + > + cpu@103 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <7>; > + }; The reg values are still wrong for the second cluster. ChenYu -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hello Maxime, Sorry for delayed response. On Mon, Oct 26, 2015 at 4:20 AM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Hi, > > On Fri, Oct 23, 2015 at 07:46:16AM +0800, Vishnu Patekar wrote: >> + memory { >> + reg = <0x40000000 0x80000000>; >> + }; >> + >> + timer { >> + compatible = "arm,armv7-timer"; >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > > Shouldn't the number of CPUs be 8? Yes, It should be 8, also need to change in gic node to 8 CPUs. No, smp support till now, still I'll change it in next patch version. > >> + clock-frequency = <24000000>; >> + arm,cpu-registers-not-fw-configured; >> + }; > > Is there some u-boot support for this SoC yet? recently, I've posted the v2 of u-boot patch. > > If so, both the memory node and the clock-frequency and > arm,cpu-registers-not-fw-configured properties are useless (and > harmful for the latter). Correct, As, timer support is added in u-boot, I'll remove these two. > >> + soc@01c00000 { > > Please remove the address. It's both wrong and useless. > >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + gic: interrupt-controller@01c81000 { >> + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; >> + reg = <0x01c81000 0x1000>, >> + <0x01c82000 0x1000>, >> + <0x01c84000 0x2000>, >> + <0x01c86000 0x2000>; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + >> + pio: pinctrl@01c20800 { >> + compatible = "allwinner,sun8i-a83t-pinctrl"; >> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > > Please align these lines with the first one, like you did for the > GIC's reg for example. Okie. > >> + reg = <0x01c20800 0x400>; >> + clocks = <&osc24M>; >> + gpio-controller; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + #gpio-cells = <3>; >> + >> + i2c0_pins_a: i2c0@0 { >> + allwinner,pins = "PH0", "PH1"; >> + allwinner,function = "i2c0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + >> + i2c1_pins_a: i2c1@0 { >> + allwinner,pins = "PH2", "PH3"; >> + allwinner,function = "i2c1"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + >> + i2c2_pins_a: i2c2@0 { >> + allwinner,pins = "PH4", "PH5"; >> + allwinner,function = "i2c2"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + >> + mmc0_pins_a: mmc0@0 { >> + allwinner,pins = "PF0", "PF1", "PF2", >> + "PF3", "PF4", "PF5"; >> + allwinner,function = "mmc0"; >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + >> + mmc1_pins_a: mmc1@0 { >> + allwinner,pins = "PG0", "PG1", "PG2", >> + "PG3", "PG4", "PG5"; >> + allwinner,function = "mmc1"; >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + >> + mmc2_8bit_pins: mmc2_8bit { >> + allwinner,pins = "PC5", "PC6", "PC8", >> + "PC9", "PC10", "PC11", >> + "PC12", "PC13", "PC14", >> + "PC15"; >> + allwinner,function = "mmc2"; >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + >> + uart0_pins_a: uart0@0 { >> + allwinner,pins = "PF2", "PF4"; >> + allwinner,function = "uart0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + >> + uart0_pins_b: uart0@1 { >> + allwinner,pins = "PB9", "PB10"; >> + allwinner,function = "uart0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; > > Are you going to use all these options? Not, only uart0_pins_a and uart0_pins_b and mmc0_pins_a will be used for now. As, these are not enabled, I don't see any harm in keeping those here. Let me know in case you want to remove, I'll do it. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux, Kernel and Android engineering > http://free-electrons.com -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi! On Mon, Nov 30, 2015 at 02:09:14AM +0800, Vishnu Patekar wrote: > >> + reg = <0x01c20800 0x400>; > >> + clocks = <&osc24M>; > >> + gpio-controller; > >> + interrupt-controller; > >> + #interrupt-cells = <3>; > >> + #gpio-cells = <3>; > >> + > >> + i2c0_pins_a: i2c0@0 { > >> + allwinner,pins = "PH0", "PH1"; > >> + allwinner,function = "i2c0"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + > >> + i2c1_pins_a: i2c1@0 { > >> + allwinner,pins = "PH2", "PH3"; > >> + allwinner,function = "i2c1"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + > >> + i2c2_pins_a: i2c2@0 { > >> + allwinner,pins = "PH4", "PH5"; > >> + allwinner,function = "i2c2"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + > >> + mmc0_pins_a: mmc0@0 { > >> + allwinner,pins = "PF0", "PF1", "PF2", > >> + "PF3", "PF4", "PF5"; > >> + allwinner,function = "mmc0"; > >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + > >> + mmc1_pins_a: mmc1@0 { > >> + allwinner,pins = "PG0", "PG1", "PG2", > >> + "PG3", "PG4", "PG5"; > >> + allwinner,function = "mmc1"; > >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + > >> + mmc2_8bit_pins: mmc2_8bit { > >> + allwinner,pins = "PC5", "PC6", "PC8", > >> + "PC9", "PC10", "PC11", > >> + "PC12", "PC13", "PC14", > >> + "PC15"; > >> + allwinner,function = "mmc2"; > >> + allwinner,drive = <SUN4I_PINCTRL_30_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + > >> + uart0_pins_a: uart0@0 { > >> + allwinner,pins = "PF2", "PF4"; > >> + allwinner,function = "uart0"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > >> + > >> + uart0_pins_b: uart0@1 { > >> + allwinner,pins = "PB9", "PB10"; > >> + allwinner,function = "uart0"; > >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > >> + }; > > > > Are you going to use all these options? > > Not, only uart0_pins_a and uart0_pins_b and mmc0_pins_a will be used for now. > As, these are not enabled, I don't see any harm in keeping those here. It bloats the DT for no particular reason. > Let me know in case you want to remove, I'll do it. Yes, please. Thanks! Maxime
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi new file mode 100644 index 0000000..e85995f --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -0,0 +1,247 @@ +/* + * Copyright 2015 Vishnu Patekar + * + * Vishnu Patekar <vishnupatekar0510@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + + */ + +#include "skeleton.dtsi" + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + interrupt-parent = <&gic>; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + cpu@100 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <4>; + }; + + cpu@101 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <5>; + }; + cpu@102 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <6>; + }; + + cpu@103 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <7>; + }; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-a83t-pinctrl"; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x01c20800 0x400>; + clocks = <&osc24M>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PH0", "PH1"; + allwinner,function = "i2c0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PH2", "PH3"; + allwinner,function = "i2c1"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "i2c2"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "mmc2"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PF2", "PF4"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + uart0_pins_b: uart0@1 { + allwinner,pins = "PB9", "PB10"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + }; +};
Allwinner A83T is new octa-core cortex-a7 SOC. This adds the basic dtsi, the clocks differs from earlier sun8i SOCs. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> --- arch/arm/boot/dts/sun8i-a83t.dtsi | 247 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 247 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi