From patchwork Tue Oct 20 08:25:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 532827 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 08DF1140180 for ; Tue, 20 Oct 2015 19:27:33 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752513AbbJTI1b (ORCPT ); Tue, 20 Oct 2015 04:27:31 -0400 Received: from conuserg009.nifty.com ([202.248.44.35]:28321 "EHLO conuserg009-v.nifty.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751623AbbJTIZN (ORCPT ); Tue, 20 Oct 2015 04:25:13 -0400 Received: from beagle.diag.org (KD036012010009.au-net.ne.jp [36.12.10.9]) (authenticated) by conuserg009-v.nifty.com with ESMTP id t9K8Ob4x008860; Tue, 20 Oct 2015 17:24:41 +0900 X-Nifty-SrcIP: [36.12.10.9] From: Masahiro Yamada To: linux-gpio@vger.kernel.org Cc: Masahiro Yamada , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] pinctrl: uniphier: set input-enable before pin-muxing Date: Tue, 20 Oct 2015 17:25:09 +0900 Message-Id: <1445329509-6252-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. Fixes: 6e9088920258 ("pinctrl: UniPhier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada Reported-by: Dai Okamura --- Hi Linus, If it is not too late, please apply this fix for Linux 4.3. Thanks, Masahiro drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 918f3b6..589872c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -539,6 +539,12 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin, unsigned reg, reg_end, shift, mask; int ret; + /* some pins need input-enabling */ + ret = uniphier_conf_pin_input_enable(pctldev, + &pctldev->desc->pins[pin], 1); + if (ret) + return ret; + reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; reg_end = reg + reg_stride; shift = pin * mux_bits % 32; @@ -563,9 +569,7 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin, return ret; } - /* some pins need input-enabling */ - return uniphier_conf_pin_input_enable(pctldev, - &pctldev->desc->pins[pin], 1); + return 0; } static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev,