From patchwork Wed Oct 14 20:07:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 530349 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B9384140157 for ; Thu, 15 Oct 2015 07:09:25 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=oCacHehE; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754600AbbJNUJL (ORCPT ); Wed, 14 Oct 2015 16:09:11 -0400 Received: from mail-wi0-f169.google.com ([209.85.212.169]:33044 "EHLO mail-wi0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932508AbbJNUHz (ORCPT ); Wed, 14 Oct 2015 16:07:55 -0400 Received: by wijp11 with SMTP id p11so10042975wij.0; Wed, 14 Oct 2015 13:07:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pJXyD4TqI8E4b3wO0Fcfylyi8SJz+g72siURhj9CxI0=; b=oCacHehE4pbX/gg8aOU9iv6EB7ehPjjCXzS9luNtZwLShBaarxzBiLuZo9V/iY9fXx Ejb7LPsUFVrRlogyqp7BMV1bXFMkHJWvy4DSxnfTpUS9CAENiSCmLr2dIHUJBiaBujVG fjDrqdbm1FmDstYzbur7eZgykQmThgyxPZjAFkeeajKddkp/lDMRgOO8ji5VD48d8Dev qAthihaK3HgvH5/ArRaltT8uFiM/fL3b8kZeWzJIjI6kdd/UWdV6R3n7PXzEh7KTp0ll rDSWMM6Px//zKwBTPT9SOpGoUkBSmePVDquIbl68IHPCTFAa+ir5BVwE0aL7R2M3Dv8M l1ug== X-Received: by 10.180.105.135 with SMTP id gm7mr28461727wib.18.1444853274219; Wed, 14 Oct 2015 13:07:54 -0700 (PDT) Received: from lmecul0520.st.com. (101.210.139.88.rev.sfr.net. [88.139.210.101]) by smtp.gmail.com with ESMTPSA id q1sm12005898wjy.31.2015.10.14.13.07.52 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Oct 2015 13:07:53 -0700 (PDT) From: Maxime Coquelin To: Linus Walleij , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, afaerber@suse.de, devicetree@vger.kernel.org, Daniel Thompson , bruherrera@gmail.com Subject: [PATCH 7/7] ARM: dts: Add USART1 pin config to STM32F429 boards Date: Wed, 14 Oct 2015 22:07:27 +0200 Message-Id: <1444853247-31114-8-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444853247-31114-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1444853247-31114-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch selects USART1 pin configuration on PA9/PA10 pins for both Eval and Disco boards. Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/stm32429i-eval.dts | 2 ++ arch/arm/boot/dts/stm32f429-disco.dts | 2 ++ arch/arm/boot/dts/stm32f429.dtsi | 13 +++++++++++++ 3 files changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 6964fc9..71fe17a 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index f0b731d..e3ce796 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -71,5 +71,7 @@ }; &usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 9e6e75c..eb3580e 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -263,6 +263,19 @@ clocks = <&rcc 0 266>; st,bank-name = "GPIOK"; }; + + usart1_pins_a: usart1@0 { + pins1 { + pinmux = ; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; + bias-disable; + }; + }; }; rcc: rcc@40023810 {